Patents by Inventor Tyler J. Weeks

Tyler J. Weeks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuits with recessed gate electrodes
    Patent number: 12165928
    Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L Hattendorf
  • Integrated circuits with recessed gate electrodes
    Patent number: 11183432
    Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
  • Integrated circuits with recessed gate electrodes
    Patent number: 10651093
    Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
  • Integrated circuits with recessed gate electrodes
    Patent number: 10020232
    Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: July 10, 2018
    Assignee: Intel Corporation
    Inventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
  • Integrated circuits with selective gate electrode recess
    Patent number: 9418898
    Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J Weeks, Mark Y. Liu, Michael L. Hattendorf
  • Integrated circuits with selective gate electrode recess
    Patent number: 8896030
    Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf