Patents by Inventor Tyler J. Weeks
Tyler J. Weeks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220044971Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: ApplicationFiled: October 19, 2021Publication date: February 10, 2022Inventors: Srijit MUKHERJEE, Christopher J. WIEGAND, Tyler J. WEEKS, Mark Y. LIU, Michael L. HATTENDORF
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Patent number: 11183432Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: GrantFiled: April 9, 2020Date of Patent: November 23, 2021Assignee: Intel CorporationInventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
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Publication number: 20200235014Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: ApplicationFiled: April 9, 2020Publication date: July 23, 2020Inventors: Srijit MUKHERJEE, Christopher J. WIEGAND, Tyler J. WEEKS, Mark Y. LIU, Michael L. HATTENDORF
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Patent number: 10651093Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: GrantFiled: June 27, 2018Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
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Publication number: 20190035690Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: ApplicationFiled: June 27, 2018Publication date: January 31, 2019Inventors: Srijit MUKHERJEE, Christopher J. WIEGAND, Tyler J. WEEKS, Mark Y. LIU, Michael L. HATTENDORF
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Patent number: 10020232Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: GrantFiled: July 27, 2016Date of Patent: July 10, 2018Assignee: Intel CorporationInventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
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Publication number: 20160372377Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: ApplicationFiled: July 27, 2016Publication date: December 22, 2016Inventors: Srijit Mukherjee, Christopher J. WIEGAND, Tyler J. WEEKS, Mark Y. LIU, Michael L. HATTENDORF
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Patent number: 9418898Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: GrantFiled: November 19, 2014Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J Weeks, Mark Y. Liu, Michael L. Hattendorf
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Publication number: 20150079776Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: ApplicationFiled: November 19, 2014Publication date: March 19, 2015Inventors: Srijit MUKHERJEE, Christopher J. WIEGAND, Tyler J WEEKS, Mark Y. LIU, Michael L. HATTENDORF
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Patent number: 8896030Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: GrantFiled: September 7, 2012Date of Patent: November 25, 2014Assignee: Intel CorporationInventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf