Abstract: The present invention relates to wave pools and diversion channels that capture high kinetic energy portions of a wave generated within the wave pool, and redirects the captured wave portions to the vicinity of wave formation, preferably timed so as reinforce a subsequently generated wave. The high kinetic energy within the diversion channel creates an additional feature in the form of an action river for riders of a wave pool to enjoy. At the same time, capturing of portions of the wave reduces the backwash of the wave and stabilizes the level of water within the wave pool, especially for embodiments with wave generators and pools capable of high volume waves. Riders may enter the diversion channel and ride from the distal, beach end of the wave pool to the proximal, wave generating end.

Abstract: A system for validating data collected in a first clock domain. A performance counter is disposed in a second clock domain to perform performance computations relative to the data. Validation circuitry is in communication with the data in order to provide to the performance counter a validation signal indicative of the validity of the data.

Abstract: In one embodiment, the invention is directed to a zeroing circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The zeroing circuit comprises logic for zeroing out a specified number of most significant bits (“MSBs”) of a selected portion of the debug data based on a mask generated by a mask generator block. A selection control signal provided to the mask generator block is operable to be decoded to a particular mask.

Abstract: In one embodiment, the invention is directed to a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The GPPC includes an AND/OR circuit connected to receive the debug data; a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a count; and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a first relationship to a compare value, wherein the AND/OR circuit activates the increment signal responsive to a selected combination of bits of an events signal being set.

Abstract: In one embodiment, the invention is directed to a data selection circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The data selection circuit is connected to receive the debug data and comprises logic for receiving the debug data as a plurality of N-bit portions of block-aligned data and outputting a designated one of the N-bit portions; and circuitry for providing to the receiving logic a control signal for designating one of the N-bit portions.

Abstract: An improved device for discharging water that is capable of efficiently generating an effective wave-like motion within a body of water. Wave generation devices based on water filled elongated tubular chambers having a substantially closed rear end and a substantially open front end and using compressed air to discharge water, such as the wave cannon, may experience operational inefficiencies from variations in quantities of compressed air. Reducing the quantity of compressed gas may result in ineffective waves and damage to the elongated tube as internal low pressure conditions collapse. A source of make-up fluid configured to mitigate internal low pressure conditions can enable effective wave generation with reduced quantities of compressed air.

Abstract: In one embodiment, the invention is directed to a match circuit for implementation in a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The match circuit comprises logic for activating a match signal when a selected N-bit portion of the debug data matches an N-bit threshold for all bits selected by an N-bit match mask (“mmask”).

Abstract: A circuit for tracking the minimum and maximum duration of an event of interest, and for tracking the minimum and maximum value of a signal of interest, is described. The circuit is connected to a counter for counting a number of clock cycles that the event of interest is active and comprises logic for detecting deactivation of the event of interest and generating a duration end signal; logic responsive to the duration end signal for capturing a value of the counter as a count value in a first circuit configuration, logic for capturing the value of the signal of interest as the count value in a second circuit configuration, logic for comparing the count value with a shadow value; and logic for updating the shadow value based on results of the comparing.

Abstract: One disclosed embodiment may comprise an application specific integrated circuit (ASIC). The ASIC includes memory that stores condition data defining conditions for enabling transitions among a plurality of states and next state data defining a next state associated with each of the respective conditions. A state machine circuit employs the condition data and the next state data to transition from a current state of the state machine circuit to a next state as a function of applying at least one condition relative to input data. The at least one condition is defined by condition data that is associated with the current state. The state machine circuit associates next state data with the at least one condition based on the current state of the state machine circuit. A control circuit provides a trigger signal in response to the current state of the state machine circuit transitioning to at least one predefined state of the plurality of states.

Abstract: One disclosed embodiment may comprise a system that includes a qualification system that qualifies data on an associated bus for capture and provides a qualification signal as a function of at least one signal that describes a characteristic of the data on the associated bus. A data capture system stores qualified data from the associated bus based on the qualification signal and a trigger signal, the trigger signal defining a capture session.

Abstract: One disclosed embodiment may comprise a system that includes a monitoring system that provides at least one signal as a function of at least some data provided on a bus. A measure of performance for the at least some data is adjusted based on the at least one signal. An analysis system is operative to perform logic analysis of the data on the bus as a function of the at least one signal.

Abstract: One disclosed embodiment may comprise a system that includes a data capture system that stores a set of data from an associated data source in response to a store signal while enabled based on a control signal. A control system provides the control signal based on a number of store cycles relative to an event to define the set of data, the number of store cycles varying based on the store signal.

Abstract: A method, system, and apparatus for testing a scalable computer system is provided. In an illustrative implementation, a system for testing a scalable computer system includes configuring a single cell on a partitionable system to create an isolated test channel. A test packet is generated and provided to the test channel. The test channel inserts the test packet into the scalable computer system via a communications link, and a response to the insertion of the test packet is monitored to determine system performance.

Abstract: A crossbar switch having a plurality of ports that allows a debug process to be performed on the switch using one of the plurality of ports to output chip status information. The switch uses a debug block to store chip status information.

Abstract: A system and method for observing the functional behavior of a target circuit. In one embodiment, a first interface, which is external with respect to the target circuit, is provided for generating behavioral definitions relative to the target circuit. A programmer module is used, responsive to the behavioral definitions, for generating a programmation file that manipulates a logic analyzer, which is embedded with respect to the target circuit. An observability tool is provided for utilizing the programmation file to observe the target circuit's functionality. A second interface, which is external with respect to the target circuit, displays results relative to observing the target circuit's functionality.

Abstract: An edge detect circuit connected to a bus carrying data is described. In one embodiment, the edge detect circuit comprises logic for detecting an edge of a raw increment signal and logic for activating an increment signal upon detection of an edge of the raw increment signal.

Abstract: A circuit for tracking the minimum and maximum duration of an event of interest is described. The circuit is connected to a counter for counting a number of clock cycles that the event of interest is active and comprises logic for detecting deactivation of the event of interest and generating a duration end signal; logic responsive to the duration end signal for comparing a count value with a shadow value; and logic for updating the shadow value based on results of the comparing.

Abstract: A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of the N outputs of the DEMUX is connected to a corresponding one of the X registers; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the registers.

Abstract: A system for validating data collected in a first clock domain. A performance counter is disposed in a second clock domain to perform performance computations relative to the data. Validation circuitry is in communication with the data in order to provide to the performance counter a validation signal indicative of the validity of the data.

Abstract: In one embodiment, the invention is directed to a zeroing circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The zeroing circuit comprises logic for zeroing out a specified number of most significant bits (“MSBs”) of a selected portion of the debug data based on a mask generated by a mask generator block. A selection control signal provided to the mask generator block is operable to be decoded to a particular mask.