Patents by Inventor Tyler Leuten

Tyler Leuten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12096566
    Abstract: Embodiments disclosed herein include a printed circuit board (PCB) with a non-uniform thickness and methods of fabricating such PCBs. In an embodiment, the PCB comprises a connector region with a top surface and a bottom surface, and a component region with a top surface and a bottom surface. In an embodiment, the bottom surface of the connector region is coplanar with the bottom surface of the component region. In an embodiment the top surface of the connector region is not coplanar with the top surface of the component region.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: September 17, 2024
    Assignee: Intel Corporation
    Inventor: Tyler Leuten
  • Patent number: 11948917
    Abstract: Embodiments described herein provide a semiconductor package comprising multiple dies encapsulated in multiple molding compounds. In one example, a semiconductor package comprises: a first die or die stack on a substrate; a first molding compound encapsulating the first die or die stack on the substrate; a second die or die stack on the first molding compound; and a second molding compound encapsulating the second die or die stack and at least one portion of the first molding compound. In this example, the first die or die stack is electrically coupled to the substrate using a first wire bond and the second die or die stack is electrically coupled to the substrate using a second wire bond. Additionally, the first molding compound encapsulates the first wire bond and the second molding compound encapsulates the second wire bond. Furthermore, a footprint of the second die overlaps a footprint of the first die.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Florence Pon, Yi Xu, James Zhang, Yuhong Cai, Tyler Leuten, William Glennan, Hyoung Il Kim
  • Patent number: 11811182
    Abstract: Embodiments disclosed herein include electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first substrate and a plurality of first conductive pads on the first substrate. In an embodiment, the electronics package further comprises a second substrate and a plurality of second conductive pads on the second substrate. In an embodiment, the electronics package further comprises a plurality of interconnects between the first and second substrate. In an embodiment, each interconnect electrically couples one of the first conductive pads to one of the second conductive pads. In an embodiment, the interconnects comprise strands of conductive material that are woven on themselves to form a mesh-like structure.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Tyler Leuten, Mohammed Rahman, Bilal Khalaf
  • Patent number: 11646253
    Abstract: Embodiments include a microelectronic package structure having a substrate with one or more substrate pads on a first side of the package substrate. A ball interconnect structure is on the substrate pad, the ball interconnect structure comprising at least 99.0 percent gold. A discrete component having two or more component terminals is on the ball interconnect structure.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventor: Tyler Leuten
  • Patent number: 11562978
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device comprises a die (18) having a bond pad (22); and a decoupling capacitor (14) mounted on the die (18) and electrically coupled to the die (18). A method for making an electronic device comprises mounting a decoupling capacitor (14) on a die (18); and electrically coupling the decoupling capacitor (14) to the die (18).
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Florence R. Pon, Tyler Leuten, John K. Yap
  • Patent number: 11495547
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of buildup layers, and where each buildup layer has fiber reinforcement. In an embodiment, the electronic package further comprises a reinforcement layer, where the reinforcement layer comprises a buildup layer and fiber reinforcement, and where an orientation of the fibers in the reinforcement layer is different than an orientation of the fibers in the package substrate.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: November 8, 2022
    Assignee: Intel Corporation
    Inventors: Florence Pon, Tyler Leuten, Maria Angela Damille Ramiso
  • Patent number: 11399434
    Abstract: Embodiments disclosed herein include modular electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first connector module having a notch on a first end and a plurality of surface mount technology (SMT) pads on a second end. In an embodiment, the electronics package further comprises a second connector module having a keyed connector on a first end and a plurality of SMT pads on a second end. In an embodiment, the electronics package further comprises a system in package (SIP) module between the first connector module and the second connector module, the component module electrically and mechanically coupled to the SMT pads of the first connector and the SMT pads of the second connector.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 26, 2022
    Inventors: Florence Pon, Tyler Leuten, Maria Angela Damille Ramiso
  • Publication number: 20220181294
    Abstract: Integrated circuit assemblies may contain various mold, fill, and/or underfill materials. As these integrated circuit assemblies become ever smaller, it becomes challenging to prevent voids from forming within these materials, which may affect the reliability of the integrated circuit assemblies. Since integrated circuit assemblies are generally formed by electrically attaching integrated circuit dice on electronic substrates, the present description proposes injecting the mold, fill, and/or underfill materials through openings formed in the electronic substrate to fill voids that may form and/or to prevent the formation of the voids altogether.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Tyler Leuten, Yi Xu, Eleanor Patricia Paras Rabadam
  • Patent number: 10910301
    Abstract: Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Min-Tih Ted Lai, Tyler Leuten, Florence R. Pon
  • Patent number: 10872880
    Abstract: BGA packages with a LGA package extension. First lands on a substrate are populated with solder balls, while only solder paste is dispensed on second lands that are surrounded by the first lands. Differences in solder stand-off may accommodate non-planarity in a package or the insertion of an LGA extension component, such as an IC or one or more discrete devices. Where an LGA extension component is attached to the second lands, solder paste may be further dispensed on third lands located on a package-side of the extension component. A BGA package is then attached to the first lands and third lands. The larger volume BGA solder connections maintaining mechanical reliability, particularly where the solder ball interconnects form a perimeter surrounding the low-volume solder interconnects.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Tyler Leuten, Min-Tih Lai
  • Publication number: 20200343221
    Abstract: Embodiments described herein provide a semiconductor package comprising multiple dies encapsulated in multiple molding compounds. In one example, a semiconductor package comprises: a first die or die stack on a substrate; a first molding compound encapsulating the first die or die stack on the substrate; a second die or die stack on the first molding compound; and a second molding compound encapsulating the second die or die stack and at least one portion of the first molding compound. In this example, the first die or die stack is electrically coupled to the substrate using a first wire bond and the second die or die stack is electrically coupled to the substrate using a second wire bond. Additionally, the first molding compound encapsulates the first wire bond and the second molding compound encapsulates the second wire bond. Furthermore, a footprint of the second die overlaps a footprint of the first die.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Inventors: Florence PON, Yi XU, James ZHANG, Yuhong CAI, Tyler LEUTEN, William GLENNAN, Hyoung Il KIM
  • Publication number: 20200119467
    Abstract: Embodiments disclosed herein include electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first substrate and a plurality of first conductive pads on the first substrate. In an embodiment, the electronics package further comprises a second substrate and a plurality of second conductive pads on the second substrate. In an embodiment, the electronics package further comprises a plurality of interconnects between the first and second substrate. In an embodiment, each interconnect electrically couples one of the first conductive pads to one of the second conductive pads. In an embodiment, the interconnects comprise strands of conductive material.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: Tyler LEUTEN, Mohammed RAHMAN, Bilal KHALAF
  • Publication number: 20200120800
    Abstract: Embodiments disclosed herein include modular electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first connector module having a notch on a first end and a plurality of surface mount technology (SMT) pads on a second end. In an embodiment, the electronics package further comprises a second connector module having a keyed connector on a first end and a plurality of SMT pads on a second end. In an embodiment, the electronics package further comprises a system in package (SIP) module between the first connector and the second connector, the component module electrically and mechanically coupled to the SMT pads of the first connector and the SMT pads of the second connector.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: Florence PON, Tyler LEUTEN, Maria Angela Damille RAMISO
  • Publication number: 20200120808
    Abstract: Embodiments disclosed herein include a printed circuit board (PCB) with a non-uniform thickness and methods of fabricating such PCBs. In an embodiment, the PCB comprises a connector region with a top surface and a bottom surface, and a component region with a top surface and a bottom surface. In an embodiment, the bottom surface of the connector region is coplanar with the bottom surface of the component region. In an embodiment the top surface of the connector region is not coplanar with the top surface of the component region.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventor: Tyler LEUTEN
  • Publication number: 20200118941
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of buildup layers, and where each buildup layer has fiber reinforcement. In an embodiment, the electronic package further comprises a reinforcement layer, where the reinforcement layer comprises a buildup layer and fiber reinforcement, and where an orientation of the fibers in the reinforcement layer is different than an orientation of the fibers in the package substrate.
    Type: Application
    Filed: October 15, 2018
    Publication date: April 16, 2020
    Inventors: Florence PON, Tyler LEUTEN, Maria Angela Damille RAMISO
  • Publication number: 20200051903
    Abstract: Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Min-Tih Ted Lai, Tyler Leuten, Florence R. Pon
  • Patent number: 10483198
    Abstract: Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Min-Tih Ted Lai, Tyler Leuten, Florence R. Pon
  • Publication number: 20190312005
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device comprises a die (18) having a bond pad (22); and a decoupling capacitor (14) mounted on the die (18) and electrically coupled to the die (18). A method for making an electronic device comprises mounting a decoupling capacitor (14) on a die (18); and electrically coupling the decoupling capacitor (14) to the die (18).
    Type: Application
    Filed: December 31, 2016
    Publication date: October 10, 2019
    Applicant: Intel Corporation
    Inventors: Florence R. Pon, Tyler Leuten, John K. Yap
  • Publication number: 20190304886
    Abstract: Embodiments include a microelectronic package structure having a substrate with one or more substrate pads on a first side of the package substrate. A ball interconnect structure is on the substrate pad, the ball interconnect structure comprising at least 99.0 percent gold. A discrete component having two or more component terminals is on the ball interconnect structure.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventor: Tyler Leuten
  • Publication number: 20190244931
    Abstract: BGA packages with a LGA package extension. First lands on a substrate are populated with solder balls, while only solder paste is dispensed on second lands that are surrounded by the first lands. Differences in solder stand-off may accommodate non-planarity in a package or the insertion of an LGA extension component, such as an IC or one or more discrete devices. Where an LGA extension component is attached to the second lands, solder paste may be further dispensed on third lands located on a package-side of the extension component. A BGA package is then attached to the first lands and third lands. The larger volume BGA solder connections maintaining mechanical reliability, particularly where the solder ball interconnects form a perimeter surrounding the low-volume solder interconnects.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Applicant: Intel Corporation
    Inventors: Tyler LEUTEN, Min-Tih LAI