Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes: first memory cells and an associated first control gate located on a first level of the apparatus; second memory cells and an associated second control gate located on a second level of the apparatus; a level of dielectric material between the first and second control gates; the second control gate including a conductive material, and a first dielectric liner and a second dielectric liner adjacent respective sides of the conductive material; the second dielectric liner including an opening adjacent a portion of the conductive material; the first dielectric liner extending continuously at the portion of the conductive material; and a conductive contact extending through the first control gate, the level of dielectric material, and the opening of the second dielectric liner and contacting the conductive material of the second control gate.

Abstract: Semiconductor devices and methods are disclosed, including memory cells/memory strings, semiconductor devices and systems. Example semiconductor devices and methods include a stack of alternating dielectric layers and conductor layers, and a vertical conductor passing between a top level of the stack and a bottom level of the stack. Lateral connections are included between a location along the vertical conductor and a selected conductor layer from the stack, wherein a direct interface is formed between the vertical conductor and the selected conductor layer.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes: first memory cells and an associated first control gate located on a first level of the apparatus; second memory cells and an associated second control gate located on a second level of the apparatus; a level of dielectric material between the first and second control gates; the second control gate including a conductive material, and a first dielectric liner and a second dielectric liner adjacent respective sides of the conductive material; the second dielectric liner including an opening adjacent a portion of the conductive material; the first dielectric liner extending continuously at the portion of the conductive material; and a conductive contact extending through the first control gate, the level of dielectric material, and the opening of the second dielectric liner and contacting the conductive material of the second control gate.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes: levels of conductive materials; levels of dielectric materials interleaved with the levels of conductive materials, the levels of conductive materials including a first conductive level and a second conductive level; a memory cell string including a pillar extending through the levels of conductive materials and the levels of dielectric materials; a first conductive contact extending through the levels of conductive materials and the levels of dielectric materials, the first conductive contact contacting the first conductive level, the first conductive level forming a first control gate associated with the memory cells; and a second conductive contact extending through the levels of conductive materials and the levels of dielectric materials, the second conductive contact contacting a second conductive level, the second conductive level forming a second control gate associated with the memory cells.