Patents by Inventor TYLER OSBORN

TYLER OSBORN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160043056
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet is over the interconnect areas of the first and the second die. Conductive vias in the dielectric sheet connect with pads of the interconnect areas. A build-up layer over the dielectric sheet includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias. The dies are mounted to a package substrate through the build-up layers, and a package cover is over the dies, the dielectric sheet, and the build-up layer.
    Type: Application
    Filed: October 19, 2015
    Publication date: February 11, 2016
    Applicant: INTEL CORPORATION
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Patent number: 9177831
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Publication number: 20150091182
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Publication number: 20080073795
    Abstract: Integrated circuit interconnection devices and methods are provided. An interconnection to connect components can comprise a first portion, a second portion, and a joining portion. The first portion can extend from a first component, and the first portion can be made with a single conductor. The second portion can extend from a second component, and the second portion can be made with the single conductor. The joining section can be disposed between the first portion and the second portion so that the first component and second component are interconnected to each other to form an interconnect. The joining section can be made of the single conductor so that the interconnect structure consists only of the single conductor. An interconnect can also be formed with two portions, and be formed to have a high-aspect ratio. Other embodiments are also claimed and described.
    Type: Application
    Filed: September 24, 2006
    Publication date: March 27, 2008
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventors: PAUL A. KOHL, ATE HE, TYLER OSBORN