Patents by Inventor Tz-Jun Kuo
Tz-Jun Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11715689Abstract: A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.Type: GrantFiled: July 13, 2020Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
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Patent number: 11551967Abstract: Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.Type: GrantFiled: May 19, 2020Date of Patent: January 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Meng-Pei Lu, Ming-Han Lee, Shin-Yi Yang, Tz-Jun Kuo
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Publication number: 20220352012Abstract: Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Inventors: Meng-Pei LU, Tz-Jun Kuo, Shin-Yi Yang, Ming-Han Lee
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Publication number: 20220262675Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tz-Jun Kuo, Chien-Hsin HO, Ming-Han LEE
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Patent number: 11322391Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.Type: GrantFiled: October 4, 2019Date of Patent: May 3, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tz-Jun Kuo, Chien-Hsin Ho, Ming-Han Lee
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Publication number: 20210366765Abstract: Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.Type: ApplicationFiled: May 19, 2020Publication date: November 25, 2021Inventors: Meng-Pei Lu, Ming-Han Lee, Shin-Yi Yang, Tz-Jun Kuo
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Publication number: 20200343177Abstract: A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
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Patent number: 10714424Abstract: A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.Type: GrantFiled: December 21, 2018Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
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Publication number: 20200035546Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.Type: ApplicationFiled: October 4, 2019Publication date: January 30, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tz-Jun KUO, Chien-Hsin HO, Ming-Han LEE
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Patent number: 10453740Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.Type: GrantFiled: August 17, 2017Date of Patent: October 22, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tz-Jun Kuo, Chien-Hsin Ho, Ming-Han Lee
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Publication number: 20190115297Abstract: A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.Type: ApplicationFiled: December 21, 2018Publication date: April 18, 2019Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
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Publication number: 20190006230Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.Type: ApplicationFiled: August 17, 2017Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tz-Jun KUO, Chien-Hsin HO, Ming-Han LEE
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Patent number: 10163786Abstract: A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.Type: GrantFiled: March 14, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
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Patent number: 9972529Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first conductive feature over a substrate, forming a dielectric layer over the first conductive feature, forming a via trench in the dielectric layer, forming a first barrier layer in the via trench. Therefore the first barrier has a first portion disposed over the dielectric layer and a second portion disposed over the first conductive feature, applying a thermal treatment to convert the first portion of the barrier layer to a second barrier layer and exposing the first conductive feature in the via trench while a portion of the second barrier layer is disposed over the dielectric layer.Type: GrantFiled: September 28, 2015Date of Patent: May 15, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
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Patent number: 9842767Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.Type: GrantFiled: June 9, 2014Date of Patent: December 12, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Han Lee, Tz-Jun Kuo, Chien-Hsin Ho, Hsiang-Huan Lee
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Publication number: 20170236750Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.Type: ApplicationFiled: May 2, 2017Publication date: August 17, 2017Inventors: Shin-Yi Yang, Ching-Fu Yeh, Tz-Jun Kuo, Hsiang-Huan Lee, Ming-Han Lee
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Publication number: 20170186685Abstract: A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.Type: ApplicationFiled: March 14, 2017Publication date: June 29, 2017Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
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Patent number: 9640431Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.Type: GrantFiled: April 25, 2016Date of Patent: May 2, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Yi Yang, Ching-Fu Yeh, Tz-Jun Kuo, Hsiang-Huan Lee, Ming-Han Lee
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Patent number: 9613856Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first conductive feature over a substrate, forming a dielectric layer over the first conductive feature, forming a trench in the dielectric layer, forming a first barrier layer in the trench, applying a thermal treatment to convert a first portion of the barrier layer to a second barrier layer, exposing the first conductive feature in the trench while a portion of the second barrier layer is disposed over the dielectric layer and forming a second conductive feature in the trench.Type: GrantFiled: September 18, 2015Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
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Publication number: 20170092536Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first conductive feature over a substrate, forming a dielectric layer over the first conductive feature, forming a via trench in the dielectric layer, forming a first barrier layer in the via trench. Therefore the first barrier has a first portion disposed over the dielectric layer and a second portion disposed over the first conductive feature, applying a thermal treatment to convert the first portion of the barrier layer to a second barrier layer and exposing the first conductive feature in the via trench while a portion of the second barrier layer is disposed over the dielectric layer.Type: ApplicationFiled: September 28, 2015Publication date: March 30, 2017Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo