Abstract: A method for writing data in parallel and a data storage system are provided. The method includes the following. A data writing performance of a first memory device and a second memory device is evaluated. A first data volume per write unit of the first memory device and a second data volume per write unit of the second memory device are determined, and the first data volume per write unit is different from the second data volume per write unit. The first memory device and the second memory device are instructed to perform a parallel data write according to the first data volume per write unit and the second data volume per write unit.

Abstract: A power control method for a memory storage device and a memory storage system are provided. The method includes configuring a power controller in a host system, controlling, by the power controller, a power gate disposed between the host system and the memory storage device, and controlling a power supply of the memory storage device from the host system by the power gate, wherein the power gate is not controlled by a Basic Input Output System (BIOS) controller of the host system.

Abstract: A temperature control method and a data storage system are disclosed. The method includes: detecting whether a memory device is in a busy status; detecting whether a temperature of the memory device is higher than a first threshold value; instructing the memory device to perform a cool down procedure in response to that the memory device is in the busy status and the temperature of the memory device is higher than the first threshold value; and instructing the memory device to stop the cool down procedure in response to that the memory device is not in the busy status and the temperature of the memory device is lower than a second threshold value.

Abstract: A computer system, a game loading method thereof and a computer readable storage medium are provided. The computer system includes a first storage, a second storage and a processor. The first storage stores multiple game files of a game. The access rate of the second storage is faster than the first storage. The processor is coupled to the first and second storages. The processor performs the game, stores corresponding game files in the first storage into the second storage according to process of the game, and access the game files stored in the second storage to continue progress of the game. Accordingly, loading time of game scene can be reduced, so as to improve gaming experience.

Abstract: A data writing method and a storage controller are provided. The data writing method includes: selecting a plurality of first dies and a plurality of second dies from a plurality of dies of the flash memory module, receiving a writing command and determining an amount of write data corresponding to the writing command, and when the amount of write data is greater than a threshold, writing in a pSLC mode the write data into the second dies.

Abstract: A power control method for a memory storage device and a memory storage system are provided. The method includes configuring a power controller in a host system, controlling, by the power controller, a power gate disposed between the host system and the memory storage device, and controlling a power supply of the memory storage device from the host system by the power gate, wherein the power gate is not controlled by a Basic Input Output System (BIOS) controller of the host system.

Abstract: A computer system and a power management method thereof are provided. The computer system includes a storage apparatus and a processor. The processor is coupled to the storage apparatus. The processor obtains a state transition time of the storage apparatus. The state transition time is the time the storage apparatus takes to enter a power state and leave the power state. The processor changes a transition tolerance time according to the state transition time. In response to an idle timeout, the processor determines whether the storage apparatus enters the power state according to a comparison result between the transition tolerance time and the state transition time. Accordingly, power consumption and performance are improved.

Abstract: A data writing method and a storage controller are provided. The data writing method includes: selecting a plurality of first dies and a plurality of second dies from a plurality of dies of the flash memory module, receiving a writing command and determining an amount of write data corresponding to the writing command, and when the amount of write data is greater than a threshold, writing in a pSLC mode the write data into the second dies.

Abstract: A computer system and a power management method thereof are provided. The computer system includes a storage apparatus and a processor. The processor is coupled to the storage apparatus. The processor obtains a state transition time of the storage apparatus. The state transition time is the time the storage apparatus takes to enter a power state and leave the power state. The processor changes a transition tolerance time according to the state transition time. In response to an idle timeout, the processor determines whether the storage apparatus enters the power state according to a comparison result between the transition tolerance time and the state transition time. Accordingly, power consumption and performance are improved.

Abstract: The present invention discloses a data storage apparatus and an operation method thereof. The data storage apparatus includes a non-volatile memory, a volatile memory coupled to the non-volatile memory, and a memory controller coupled to the non-volatile memory and the volatile memory. The memory controller is configured to perform following operations: receiving a modern standby notification from a host; and updating a second mapping table stored in the non-volatile memory according to a number of flags and a first mapping table stored in the volatile memory.

Abstract: A storing method is provided. The storing method includes: receiving a driving instruction by a host, wherein the driving instruction triggers a driver to collect a user information, and the driver generates a hit rate information according to the user information and generates a mapping table according to the hit rate information; receiving the mapping table from the driver by a processing unit of a storage device, wherein the storage device does not have any dynamic random access memory (DRAM); storing the mapping table in a static random access memory (SRAM); storing a plurality of storing data in a number of NAND flash memories, wherein when the host receives an accessing instruction, the processing unit reads the mapping table in the SRAM to find the storing data corresponding to the accessing instruction.

Abstract: A storage system including a random access memory, a hard disk, a non-volatile memory and a processing circuit is provided. The hard disk includes a media cache. When the processing circuit is to store data in the random access memory to the hard disk, the data in the random access memory are firstly stored to the non-volatile memory. Afterwards, the data in the non-volatile memory are directly written to a number of continuous sectors in the hard disk without being stored in the media cache of the hard disk.

Abstract: A computer system, a game loading method thereof and a computer readable storage medium are provided. The computer system includes a first storage, a second storage and a processor. The first storage stores multiple game files of a game. The access rate of the second storage is faster than the first storage. The processor is coupled to the first and second storages. The processor performs the game, stores corresponding game files in the first storage into the second storage according to process of the game, and access the game files stored in the second storage to continue progress of the game. Accordingly, loading time of game scene can be reduced, so as to improve gaming experience.

Abstract: The present invention discloses a data storage apparatus and an operation method thereof. The data storage apparatus includes a non-volatile memory, a volatile memory coupled to the non-volatile memory, and a memory controller coupled to the non-volatile memory and the volatile memory. The memory controller is configured to perform following operations: receiving a modern standby notification from a host; and updating a second mapping table stored in the non-volatile memory according to a number of flags and a first mapping table stored in the volatile memory.

Abstract: A storage system including a random access memory, a hard disk, a non-volatile memory and a processing circuit is provided. The hard disk includes a media cache. When the processing circuit is to store data in the random access memory to the hard disk, the data in the random access memory are firstly stored to the non-volatile memory. Afterwards, the data in the non-volatile memory are directly written to a number of continuous sectors in the hard disk without being stored in the media cache of the hard disk.

Abstract: A storing method is provided. The storing method includes: receiving a driving instruction by a host, wherein the driving instruction triggers a driver to collect a user information, and the driver generates a hit rate information according to the user information and generates a mapping table according to the hit rate information; receiving the mapping table from the driver by a processing unit of a storage device, wherein the storage device does not have any dynamic random access memory (DRAM); storing the mapping table in a static random access memory (SRAM); storing a plurality of storing data in a number of NAND flash memories, wherein when the host receives an accessing instruction, the processing unit reads the mapping table in the SRAM to find the storing data corresponding to the accessing instruction.

Abstract: A control method for a non-volatile memory in a computer system is provided. The computer system includes a central processing unit; a system memory; a first memory controller; and a storage device including a non-volatile memory and a second memory controller for controlling access to the non-volatile memory. The method includes the steps of: utilizing the first memory controller to divide the system memory into a first data pool and a second data pool, wherein the first data pool stores temporary data for accessing the storage device by the central processing unit, and the second data pool stores flash translation layer data for use by the second memory controller; and when the central processing unit is to access the storage device, utilizing the second memory controller to access the non-volatile memory according to the flash translation layer data from the second data pool.

Abstract: An electronic device includes a first storage unit, a second storage unit and a control unit. The first storage unit stores the cache of the data. The second storage unit stores the data. The control unit calculates a first ratio of the cache corresponding to the data according to the capacity of the first storage unit. The control unit sends a distribution signal to the processing unit when the control unit reads the data from the second storage unit. The processing unit obtains a first distribution result corresponding to the cache according to the first ratio, and stores the cache to the first storage unit according to the first distribution result.

Abstract: A control method for a non-volatile memory in a computer system is provided. The computer system includes a central processing unit; a system memory; a first memory controller; and a storage device including a non-volatile memory and a second memory controller for controlling access to the non-volatile memory. The method includes the steps of: utilizing the first memory controller to divide the system memory into a first data pool and a second data pool, wherein the first data pool stores temporary data for accessing the storage device by the central processing unit, and the second data pool stores flash translation layer data for use by the second memory controller; and when the central processing unit is to access the storage device, utilizing the second memory controller to access the non-volatile memory according to the flash translation layer data from the second data pool.

Abstract: An electronic apparatus and a power management method for a solid state disk thereof are provided. The solid state disk includes a controller and multiple memory dies which are separated into multiple channels. In the method, the solid state disk uses the channels corresponding to one of at least one power state to provide parallel data processing, in which the at least one power state is set in the controller of the solid state disk, each power state only uses a portion of the channels to provide parallel data processing at one time, and a quantity of the channels used by the at least one power state is different.