Abstract: Apparatus and method for hibernating part of a memory device are disclosed. A memory device may seek to reduce its power consumption by entering deep power down (DPD) mode. In DPD mode, power to a section of volatile memory in the memory device may be removed. To that end, the memory device stores in non-volatile memory all of the data stored in the section of volatile memory. The data stored in non-volatile memory is accessed upon exiting DPD mode. Upon subsequent entries into DPD mode, a differential, between the data stored in non-volatile memory and the data currently stored in the section of volatile memory subject to power removal, is generated and stored in non-volatile memory. Upon exit of the DPD mode, the data stored in non-volatile memory and the differential are used to recreate the data stored in volatile memory at entry into DPD mode.

Abstract: In one embodiment, a memory system is provided comprising a volatile memory, a non-volatile memory, and an error correction code (ECC) module. The ECC module is configured to encode, decode, and correct data stored in the volatile memory when the memory system enters and exits a sleep mode and is further configured to encode, decode, and correct data stored in the non-volatile memory when the memory system is in an active mode.

Abstract: A memory system and method for securing volatile memory during sleep mode using the same ECC module used to secure non-volatile memory during active mode are provided. In one embodiment, a memory system is provided comprising a volatile memory, a non-volatile memory, and an error correction code (ECC) module. The ECC module is configured to encode, decode, and correct data stored in the volatile memory when the memory system enters and exits a sleep mode and is further configured to encode, decode, and correct data stored in the non-volatile memory when the memory system is in an active mode. Other embodiments are possible.