Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.

Abstract: A semiconductor device includes an analog voltage regulator and an integrated circuit module. The analog voltage regulator generates a regulated output voltage. The integrated circuit module generates an analog sense voltage based on the regulated output voltage and includes integrated circuit dies, a first sensor, second sensors, and a digital voltage offset controller (DVOC). The first sensor generates a digital reference voltage based on an analog reference voltage. The second voltage sensors detect voltages at predetermined locations on the integrated circuit dies. The DVOC generates a digital offset voltage substantially equal to the difference between the digital reference voltage and the voltage detected by a selected one of the second voltage sensors. The regulated output voltage is based on an unregulated input voltage, the analog sense voltage, and the digital offset voltage.

Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.

Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.

Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.

Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.

Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.

Abstract: A voltage regulator includes a control circuit configured to output a plurality of enable signals, and a power stage including a plurality of phase circuits. Each phase circuit of the plurality of phase circuits includes a node, an inductor coupled between the node and an output node of the voltage regulator, a plurality of p-type transistors coupled between the node and a power supply node of the voltage regulator, and a plurality of n-type transistors coupled between the node and a reference node of the voltage regulator. Each phase circuit of the plurality of phase circuits is configured to, responsive to the plurality of enable signals, selectively couple the node to the power supply node through a first subset or all of the plurality of p-type transistors, and selectively couple the node to the reference node through a second subset or all of the plurality of n-type transistors.

Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.

Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.

Abstract: A semiconductor package includes a first die comprising a voltage regulator that has a first input and a second input. The semiconductor package includes a second die coupled to the first die and comprising a first load circuit. The voltage regulator is configured to provide a regulated voltage to the first load circuit through a first through via structure based on a first voltage received through the first input and a second voltage received from the first load circuit through a second through via structure. The first voltage is a constant reference voltage, and the second voltage is a first signal sensed from the first load circuit.

Abstract: Disclosed herein are related to an integrated circuit including multiple dies stacked along a direction. In one aspect, the integrated circuit includes a first die, a second die, and a third die stacked along the direction. In one aspect, the first die includes a first interface circuit to generate a signal. In one aspect, the second die includes a second interface circuit to receive the signal from the first interface circuit and generate a replicate signal of the signal. In one aspect, the third die includes a third interface circuit to receive the replicate signal from the second interface circuit.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.

Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.