Abstract: A pixel cell for a CMOS image sensor includes an isolation structure that isolates a pixel transistor region from a pixel photodiode region. On a front side of the image sensor, the isolation structure includes a first shallow trench isolation (STI) structure, a second STI structure and a semiconductor region between the first STI structure and the second STI structure, and an implant region formed from a p-type semiconductor that is in contact with the semiconductor region and extends toward a backside of the image sensor. The semiconductor region is formed from the first type semiconductor. On a backside of the image sensor, the isolation structure includes a trench isolation structure extending from the backside toward the front side and that contacts the implant region.

Abstract: A pixel for an image sensor is disclosed that includes a photodiode, a thin-film layer and a reflective layer. The photodiode includes a first side and a second side that is opposite the first side, and receives incident light on the first side. The thin-film layer is formed on the first side of the photodiode and provides a unidirectional phase-shift to light passing from the photodiode to the thin-film layer. The thin-film layer has a refractive index that less than a refractive index of material forming the photodiode. The unidirectional phase-shift may be a unidirectional it phase shift at a target near-infrared light wavelength. The reflective layer is formed on the second side of the photodiode and reflects light passing from the photodiode to the reflective layer toward the first side of the photodiode. The reflective layer may be a thin-film layer, a Distributed Bragg Reflector layer, or a metal.

Abstract: The present disclosure relates to a method and system for time-of-flight detection. There may be two or more photodetectors in a photodetector circuit that capture photon activity. There is logic that processes the responses of the photodetectors and returns the leading edge of the arrival of the first photon and the leading edge of the arrival of the last photon, if at least two photons are received during an overlapping pulse width.

Abstract: The present disclosure relates to a method and system for imaging a scene. The method includes generating a shutter pattern and applying the shutter pattern to a photodetector array. The system includes a sensor architecture in three dimensions, where elements of the sensor architecture are stacked in two or more layers. Some elements of the sensor architecture include a photodetector array, register array, a generator to generate shutter patterns, readout circuitry, and an ISP.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to row control circuitry and column readout circuitry. An image pixel in the array may include a charge integration portion having a photodiode, a floating diffusion region, and a capacitor coupled to the floating diffusion region and may include a voltage-domain sampling portion having three capacitors. High light and low light image level and reset level signals may be sampled and stored at the voltage-domain sampling portion before being readout to the column readout circuitry during a readout operation. The high light reset level signal may be sampled and stored during the readout operation.

Abstract: This disclosure provides methods and apparatuses for annealing an oxide semiconductor in a thin film transistor (TFT). In one aspect, the method includes providing a substrate with a partially fabricated TFT structure formed on the substrate. The partially fabricated TFT structure can include an oxide semiconductor layer and a dielectric oxide layer on the oxide semiconductor layer. The oxide semiconductor layer is annealed by heating the dielectric oxide layer with an infrared laser under ambient conditions to a temperature below the melting temperature of the oxide semiconductor layer. The infrared laser radiation can be substantially absorbed by the dielectric oxide layer and can remove unwanted defects from the oxide semiconductor layer at an interface in contact with the dielectric oxide layer.

Abstract: This disclosure provides systems, methods and apparatus for measuring a temperature of a display. In one aspect, a circuit may use one or more stages of diodes or diode-connected transistors providing the functionality of diodes. Each stage may include the functionality of diodes in opposite directions. A direct current (DC) current source or an alternating current (AC) voltage source may be applied to the diodes or diode-connected transistors to measure the temperature of the display.

Abstract: This disclosure provides methods and apparatuses for annealing an oxide semiconductor in a thin film transistor (TFT). In one aspect, the method includes providing a substrate with a partially fabricated TFT structure formed on the substrate. The partially fabricated TFT structure can include an oxide semiconductor layer and a dielectric oxide layer on the oxide semiconductor layer. The oxide semiconductor layer is annealed by heating the dielectric oxide layer with an infrared laser under ambient conditions to a temperature below the melting temperature of the oxide semiconductor layer. The infrared laser radiation can be substantially absorbed by the dielectric oxide layer and can remove unwanted defects from the oxide semiconductor layer at an interface in contact with the dielectric oxide layer.

Abstract: This disclosure provides apparatuses and methods for fabricating TFTs and storage capacitors on a substrate. In one aspect, an apparatus includes a TFT and a storage capacitor, where the TFT includes a first metal layer, a second metal layer, and a semiconductor layer, where the semiconductor layer is protected by a first etch stop layer and a second etch stop layer. The storage capacitor includes the second etch stop layer as a dielectric between the first metal layer and the second metal layer. In another aspect, an apparatus includes a TFT and a storage capacitor, where the TFT includes a first metal layer, a dielectric layer, and a semiconductor layer, where the semiconductor layer is protected by an etch stop layer. The storage capacitor includes the dielectric layer as a dielectric between the first metal layer and the semiconductor layer.

Abstract: This disclosure provides systems, methods and apparatus for a thin film transistor (TFT) device on a substrate. In one aspect, the TFT device includes a gate electrode, an oxide semiconductor layer, and a gate insulator between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes at least two metal oxides, with the two metal oxides having a varying concentration relative to one another between a lower surface and an upper surface of the oxide semiconductor layer. The TFT device also includes a source metal adjacent to a portion of the oxide semiconductor layer and a drain metal adjacent to another portion of the oxide semiconductor layer. The composition of the oxide semiconductor layer can be precisely controlled by a sequential deposition technique using atomic layer deposition (ALD).

Abstract: This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load.

Abstract: This disclosure provides systems, methods and apparatus for a thin film transistor (TFT) device on a substrate. In one aspect, the TFT device includes a gate electrode, an oxide semiconductor layer, and a gate insulator between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes at least two metal oxides, with the two metal oxides having a varying concentration relative to one another between a lower surface and an upper surface of the oxide semiconductor layer. The TFT device also includes a source metal adjacent to a portion of the oxide semiconductor layer and a drain metal adjacent to another portion of the oxide semiconductor layer. The composition of the oxide semiconductor layer can be precisely controlled by a sequential deposition technique using atomic layer deposition (ALD).

Abstract: This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load.