Abstract: An impedance calibration circuit includes a variable impedance circuit, a detection circuit and a control circuit. The variable impedance circuit includes conduction paths connected in parallel between an output terminal and a supply terminal coupled to a first supply voltage. The variable impedance circuit is configured to adjust an impedance at the output terminal by enabling one or more of the conduction paths according to a calibration code. The detection circuit is configured to detect a change in impedance of the conduction paths by applying a second supply voltage to a reference terminal through a detection path, and accordingly generate an input voltage at the reference terminal. An electric potential of the second supply voltage is equal to an electric potential of the first supply voltage. The control circuit is configured to compare the input voltage with reference voltages to generate the calibration code.

Abstract: A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

Abstract: A conductive structure for electronic device includes at least a first conductor, at least a second conductor and a conductive material for connecting the first conductor and the second conductor.

Abstract: A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

Abstract: An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal.

Abstract: A method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board includes utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned in a center area of the die; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of first-layer traces being routed in a first layer of the multi-layer circuit board; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of second-layer traces being routed in a second layer of the multi-layer circuit board; routing the plurality of first-layer traces straight away from the die; and routing the plurality of second-layer traces with a turn not to be vertically underneath the first-layer traces.

Abstract: An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal.

Abstract: An apparatus and a method of controlling clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of phase intervals therebetween. A predetermined phase angle is divided by the number of the output signals to generate one of the phase intervals. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal. The phase detector connected to the first fine calibration unit is used to detect a phase difference between the reference and the feedback signal and outputting an indicating signal corresponding to the phase difference between the reference and the feedback signal.

Abstract: A method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board includes utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned in a center area of the die; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of first-layer traces being routed in a first layer of the multi-layer circuit board; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of second-layer traces being routed in a second layer of the multi-layer circuit board; routing the plurality of first-layer traces straight away from the die; and routing the plurality of second-layer traces with a turn not to be vertically underneath the first-layer traces.

Abstract: A routing method for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer circuit board. The multi-layer circuit board includes at least a first layer and a second layer. The method includes arranging the plurality of bumper pads based on a plurality of triangle units, routing a plurality of signal traces out of a plurality of corresponding bumper pads of in the first layer, routing a plurality of signal traces out of a plurality of corresponding bumper pads in the second layer not to be vertically parallel with the plurality of signal traces routed in the first layer, and arranging a plurality of shielding traces among the plurality of signal traces in the first layer and in the second layer.

Abstract: The present invention provides a multi-stage delay clock generator including: a plurality of delay cells, each delay cell generating a delay signal to a subsequent delay cell in response to a delayed clock signal from a preceding delay cell and a delay control signal where a first delay cell among the plurality of delay cells receives an external clock signal, and each subsequent delay cell comprises a smaller delay step than the current delay cell; a phase detector, responsive to the external clock signal and a feedback clock signal, for generating a lock control signal; an integrator, responsive to the lock control signal, for generating the delay control signal; and a control unit for programming the delay cells.

Abstract: The present invention provides a multi-stage delay clock generator including: a plurality of delay cells, each delay cell generating a delay signal to a subsequent delay cell in response to a delayed clock signal from a preceding delay cell and a delay control signal where a first delay cell among the plurality of delay cells receives an external clock signal, and each subsequent delay cell comprises a smaller delay step than the current delay cell; a phase detector, responsive to the external clock signal and a feedback clock signal, for generating a lock control signal; an integrator, responsive to the lock control signal, for generating the delay control signal; and a control unit for programming the delay cells.

Abstract: A routing method for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer circuit board. The multi-layer circuit board includes at least a first layer and a second layer. The method includes arranging the plurality of bumper pads based on a plurality of triangle units, routing a plurality of signal traces out of a plurality of corresponding bumper pads of in the first layer, routing a plurality of signal traces out of a plurality of corresponding bumper pads in the second layer not to be vertically parallel with the plurality of signal traces routed in the first layer, and arranging a plurality of shielding traces among the plurality of signal traces in the first layer and in the second layer.

Abstract: The present invention relates to a quasi-synchronous multi-stage event synchronization apparatus by a phase lock loop (PLL) control circuit and a quasi-synchronous multi-stage synchronizer to tolerate clock uncertainty and speed up the synchronizing process between the asynchronous digital circuits from producing-end to consuming-end in the computer system. The phase lock loop (PLL) control circuit generates a pair of well-controlled clocks, PDU_CLK, CSM_CLK, assigned to producing-end and consuming-end and a pair of clock phase indicating signals, PDU_SYNC_PULSE, CSM_SYNC_PULSE, associated with the pair of well-controlled clocks. The quasi-synchronous multi-stage synchronizer routes the series of sync events into a synchronization stage with minimal synchronization delay from producing-end to consuming-end.