Patents by Inventor Tze On Hui

Tze On Hui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120109
    Abstract: A semiconductor structure includes a metal gate structure and an isolation structure adjacent to the metal gate structure. The isolation structure includes a first dielectric layer, a second dielectric layer over the first dielectric layer and a third dielectric layer over the second dielectric layer. The first dielectric layer includes carbon of a first concentration, the second dielectric layer includes carbon of a second concentration, and the third dielectric layer includes carbon of a third concentration. The third concentration is greater than the second concentration, and the second concentration is greater than the first concentration.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: CHUN-YI CHANG, CHIA-HUI LIN, TAI-CHUN HUANG, TZE-LIANG LEE
  • Patent number: 12271113
    Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Ming-Hui Weng, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Patent number: 12272554
    Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Lin Wei, Ming-Hui Weng, Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Yahru Cheng, Jr-Hung Li, Ching-Yu Chang, Tze-Liang Lee, Chi-Ming Yang
  • Publication number: 20250087528
    Abstract: A method includes forming a gate stack, and etching the gate stack to form a trench penetrating through the gate stack. A dielectric isolation region underlying the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench. The method includes performing a first deposition process to form a first dielectric layer extending into the trench and lining sidewalls of the first portion and the second portion of the gate stack, and performing a second deposition process to form a second dielectric layer on the first dielectric layer. The second dielectric layer fills the trench. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant greater than the first dielectric constant.
    Type: Application
    Filed: January 2, 2024
    Publication date: March 13, 2025
    Inventors: Yunn-Shiuan Liu, Li-Fong Lin, Chia-Hui Lin, Tze-Liang Lee
  • Patent number: 12222643
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.
    Type: Grant
    Filed: October 22, 2022
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Ming-Hui Weng, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Publication number: 20170187585
    Abstract: Technologies for validating operations of devices include a host computing device. The host computing device validates the functionality of a system that includes a gateway device that is communicatively coupled to at least one sensor device. The host computing device transmits validation instructions to the gateway device to perform at least one function with respect to the at least one sensor device that is communicatively coupled to the gateway device. The host computing device also receives test data from the gateway device after transmitting the validation instructions, analyzes the test data to determine whether the system passed at least one of a functional test and a regression test, profiles the test data at least by characterizing at least one sensor data packet included in the test data, and generates a report that indicates a status of the system, based on the analysis and the profile. Other embodiments are described.
    Type: Application
    Filed: December 26, 2015
    Publication date: June 29, 2017
    Inventors: Tze-Hui Yew, Peng Peng Leim, Jiin Ming Khoo
  • Patent number: 9193359
    Abstract: A vehicle system for a vehicle with an occupant is provided. The system includes a seat assembly; a sensor group associated with the seat assembly and configured to collect data about physical characteristics of the occupant of the seat assembly; and a control module coupled to the sensor group and configured to identify the occupant based on the collected data about the physical characteristics of the occupant.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: November 24, 2015
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Tze On Hui, Brian T. Timmermann, Daniel T. Cohen
  • Publication number: 20150045984
    Abstract: A vehicle system for a vehicle with an occupant is provided. The system includes a seat assembly; a sensor group associated with the seat assembly and configured to collect data about physical characteristics of the occupant of the seat assembly; and a control module coupled to the sensor group and configured to identify the occupant based on the collected data about the physical characteristics of the occupant.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, LLC
    Inventors: TZE ON HUI, BRIAN T. TIMMERMANN, DANIEL T. COHEN
  • Patent number: 8695164
    Abstract: A check link assembly for positioning a vehicle closure has a selectively positionable detent feature. The check link assembly includes an elongated link having a distal end. At least one cover is attachable to the link in a first orientation and in a second orientation. The cover has a first end, a second end, and a contoured surface between the first end and the second end. At least one member is biased against the link and is configured to ride against the contoured surface of the cover. The contoured surface at least partially defines a detent feature that interferes with the biased member to increase resistance to relative movement of the link and the biased member, thereby establishing a stop position. The detent feature is further from the distal end of the link when the cover is in the first orientation than when the cover is in the second orientation.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: April 15, 2014
    Assignee: GM Global Technology Operations LLC
    Inventors: Balakrishna Chinta, Raymond R. Lipowski, Tze On Hui
  • Publication number: 20130318743
    Abstract: A check link assembly for positioning a vehicle closure has a selectively positionable detent feature. The check link assembly includes an elongated link having a distal end. At least one cover is attachable to the link in a first orientation and in a second orientation. The cover has a first end, a second end, and a contoured surface between the first end and the second end. At least one member is biased against the link and is configured to ride against the contoured surface of the cover. The contoured surface at least partially defines a detent feature that interferes with the biased member to increase resistance to relative movement of the link and the biased member, thereby establishing a stop position. The detent feature is further from the distal end of the link when the cover is in the first orientation than when the cover is in the second orientation.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 5, 2013
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Balakrishna Chinta, Raymond R. Lipowski, Tze On Hui