Abstract: A sense amplifier reference is generated with the same memory cell columns as data cells in order to match signal paths between the data and reference signals. Each row of data memory cells may have a corresponding set of reference cells, which greatly reduces the number of data cells supported by a reference, and in turn reduces the impact of process variations. A memory array may include data columns, a first reference column in the memory array configured to provide a logic 0 reference signal, and a second reference column in the memory array configured to provide a logic 1 reference signal. A circuit is configured to combine at least the logic 0 reference signal and the logic 1 reference signal to generate a reference signal for a sense amplifier to identify the data signal provided from the data columns.

Abstract: A selector for a memory cell in a memory array may operate by opening different conductive paths to high and low voltages during set and reset operations. A first transistor may open a conductive path between a high voltage and a terminal of the memory element during a reset operation. Similarly, a second transistor may open a conductive path between a low voltage and the terminal of the memory element during a set operation. Some implementations may add a third transistor in series with the first transistor and a fourth transistor in series with the second transistor. The gates of the third and fourth transistors may be biased at a voltage that is about halfway between the low and high voltages. This selector may use smaller transistors while still facilitating high-voltage set and reset operations on resistive memory elements.

Abstract: A sense amplifier reference is generated with the same memory cell columns as data cells in order to match signal paths between the data and reference signals. Each row of data memory cells may have a corresponding set of reference cells, which greatly reduces the number of data cells supported by a reference, and in turn reduces the impact of process variations. A memory array may include data columns, a first reference column in the memory array configured to provide a logic 0 reference signal, and a second reference column in the memory array configured to provide a logic 1 reference signal. A circuit is configured to combine at least the logic 0 reference signal and the logic 1 reference signal to generate a reference signal for a sense amplifier to identify the data signal provided from the data columns.

Abstract: Various arrangements for performing successive vector-matrix multiplication may include sequentially performing a first vector-matrix multiplication operation for each bit-order of values in an input vector. The first vector-matrix multiplication operation for each bit-order may generate an analog output. For each analog output generated by the vector-matrix multiplication operation, an analog output may be converted into one or more digital bit values, and the one or more digital bit values may be sent to a second vector-matrix multiplication operation.

Abstract: Various arrangements for performing vector-matrix multiplication are provided here. Digital input vectors that include binary-encoded values can be converted into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs). Using an analog vector matrix multiplier, a vector-matrix multiplication operation can be performed using a weighting matrix for each bit-order of the plurality of analog signals. For each performed vector-matrix multiplication operation, a bit-ordered indication of an output of the analog vector matrix multiplier may be stored. A bit-order weighted summation of the sequentially performed vector-matrix multiplication operation may be performed.

Abstract: A memory circuit may include a memory array, and the memory array may include a plurality of data columns. The plurality of data columns may be configured to store data bits and provide data signals when selected by a read operation. The memory array may also include one or more reference columns distributed in the memory array and configured to provide a reference signal. The reference signal may track with process, voltage, and temperature variations that are specific to the memory array, and may be used to remove a common signal component and adjust the signal level to distinguish between logic 0 and logic 1 data signals.

Abstract: Various arrangements for performing successive vector-matrix multiplication may include sequentially performing a first vector-matrix multiplication operation for each bit-order of values in an input vector. The first vector-matrix multiplication operation for each bit-order may generate an analog output. For each analog output generated by the vector-matrix multiplication operation, an analog output may be converted into one or more digital bit values, and the one or more digital bit values may be sent to a second vector-matrix multiplication operation.

Abstract: A memory circuit may include a memory array, and the memory array may include a plurality of data columns. The plurality of data columns may be configured to store data bits and provide data signals when selected by a read operation. The memory array may also include one or more reference columns distributed in the memory array and configured to provide a reference signal. The reference signal may track with process, voltage, and temperature variations that are specific to the memory array, and may be used to remove a common signal component and adjust the signal level to distinguish between logic 0 and logic 1 data signals.

Abstract: Various arrangements for performing vector-matrix multiplication are provided here. Digital input vectors that include binary-encoded values can be converted into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs). Using an analog vector matrix multiplier, a vector-matrix multiplication operation can be performed using a weighting matrix for each bit-order of the plurality of analog signals. For each performed vector-matrix multiplication operation, a bit-ordered indication of an output of the analog vector matrix multiplier may be stored. A bit-order weighted summation of the sequentially performed vector-matrix multiplication operation may be performed.

Abstract: A memory circuit includes a memory array with one or more reference columns providing a reference signal and a data column providing a data signal when selected by a read operation. The memory circuit also includes a first circuit that removes a common signal component from the reference signal and from the data signal, along with a second circuit that adjusts the reference signal to be between a logic 1 signal level and a logic 0 signal level. The memory circuit also includes a sense amplifier that determines whether the data signal represents a logic 1 or a logic 0 using the reference signal after the common signal component is removed and after being adjusted, along with the data signal after having the common signal component removed.

Abstract: The present invention discloses a voltage shifter capable of interfacing between two circuitry each is operating in different voltage range. The voltage shifter comprises an input buffer for converting an external input signal switching within a high voltage range to an internal input signal switching within a low voltage range, an output driver for converting an internal output signal switching within the low voltage range to an external output signal switching within the high voltage range; and a reference voltage generator for generating a reference voltage to the input buffer and the output driver. In addition, the voltage shifter is designed such that each of the transistors within is protected against voltage breakdown so that the voltage shifter can be built by transistors using the low voltage process.

Abstract: An output buffer circuit for preconditioning an output signal at an output node so as to provide a higher speed of operation and less ground bounce noise includes an output buffer stage, a precondition feedback circuit, an output predriver, an output tristate control circuit, and an output state retention circuit. The output pre-driver with input equalization, which is also part of precondition control, combined with the output buffer stage designed with its threshold voltage matching component's input and output threshold voltage such that the output feedback, which bring the output and the input nodes of the output buffer stage together, will drive the output level to the threshold point enabled by the precondition signals before the data input signals arrive. The output buffer noise can be reduced by slowly driving output level to the output threshold point about three to four nanoseconds earlier than the data input signals arrive.

Abstract: A bipolar/CMOS ECL-to-CMOS conversion circuit for receiving ECL differential input signals and for converting the ECL input signals to CMOS complementary output signals, includes, a first output stage (20), a second output signal (22), a first base drive circuit (24), a second base drive circuit (26), a third base drive circuit (28), and a fourth base drive circuit (30). The first and second output stages are formed of bipolar transistors, and the first through fourth base drive circuits ar formed of CMOS transistors. The bipolar transistors and CMOS transistors are merged in a common semiconductor substrate in order to form the conversion circuit which has high current drive capabilities and low propagation delay regardless of variations in temperature and process corners.

Abstract: A bipolar/CMOS decoder circuit for providing a decoded output signal includes a plurality of pull-up gate circuits (14a) and a pull-down circuit (16). Each of the gate circuite (14a) is formed of a pull-up P-channel MOS transistor (P1), a pull-down N-Channel MOS transistor (N1), and a pull-up bipolar transistor (Q1). The pull-down circuit (16) is formed of a single pull-down current source, N-channel MOS transistor (N.0.). The bipolar transistors and CMOS transistors are merged in a common semiconductor substrate in order to form the decoder circuit which has a high noise margin and low pattern sensitivity even with a large number of inputs.

Abstract: A bipolar/CMOS regulator circuit for generating a CMOS gate-controlling voltage, which varies favorably with temperature, power supply voltage and process corner so as to yield a well-controlled CMOS current includes a bipolar bandgap regulator circuit portion (12) and a conversion circuit portion (14). The conversion circuit portion (14) is formed of a current mirror section (18), a current source section (20) and an output section (22).

Abstract: A bipolar/CMOS read/write control and sensing circuit is provided for use with MOS memory cells in which data can be written into and sensed in the memory cells at high speeds. The MOS memory cell is coupled with a word line and between first and second bit lines at corresponding first and second sense nodes. The control and sensing circuit includes a bit-line clamping network which is responsive to an output control signal for clamping the first and second bit lines during a read operation so as to present a low impedance thereby decreasing the read time and for unclamping of the first and second bit lines during a write operation so as to present a high impedance which reduces the write time.

Abstract: Load resistors are connected in series between the PNP portions of the SCRs and the upper word-line. The load presented to the NPN portions of the SCRs is thus a composite formed of a PNP transistor in series with a resistor. The resistor causes a downward shift of voltage due to IR drop on the ON side of the cell and provides a dramatic improvement in writing speed. During a write operation, the IR drop across the resistor on the ON side of the cell collapses as current declines, and the consequent rise in voltage is coupled to the low base line, significantly shortening the time required to raise its voltage sufficiently to securely write the cell.