Patents by Inventor Tzo Hung Luo

Tzo Hung Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10679859
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Yu-Lin Liu, Ming-Hsien Lin, Tzo-Hung Luo
  • Publication number: 20190148153
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.
    Type: Application
    Filed: December 14, 2018
    Publication date: May 16, 2019
    Inventors: Chung-Liang Cheng, Yu-Lin Liu, Ming-Hsien Lin, Tzo-Hung Luo
  • Patent number: 10170322
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Yu-Lin Liu, Ming-Hsien Lin, Tzo-Hung Luo
  • Patent number: 9748290
    Abstract: Embodiments of mechanisms for forming an image sensor device structure are provided. The image sensor device structure includes a substrate and a transfer transistor formed on the substrate. The image sensor device structure also includes a floating node formed in the substrate and a photosensitive element formed in the substrate. The transfer transistor is formed between the floating node and the photosensitive element, and the photosensitive element includes a first doping region with a lateral doping gradient.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yueh-Chuan Lee, Tzo-Hung Luo
  • Patent number: 9653497
    Abstract: A manufacturing method of a sensing integrated circuit including the following acts. A plurality of transistors are formed. At least one dielectric layer is formed on or above the transistors. A plurality of connecting structures are formed in the dielectric layer. The connecting structures are respectively and electrically connected to the transistors. A plurality of separated conductive wells are respectively formed in electrical contact with the connecting structures.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: May 16, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzo-Hung Luo, Chin-Hung Chiang
  • Publication number: 20150380446
    Abstract: A manufacturing method of a sensing integrated circuit including the following acts. A plurality of transistors are formed. At least one dielectric layer is formed on or above the transistors. A plurality of connecting structures are formed in the dielectric layer. The connecting structures are respectively and electrically connected to the transistors. A plurality of separated conductive wells are respectively formed in electrical contact with the connecting structures.
    Type: Application
    Filed: September 9, 2015
    Publication date: December 31, 2015
    Inventors: Tzo-Hung LUO, Chin-Hung CHIANG
  • Patent number: 9171873
    Abstract: A manufacturing method of a sensing integrated circuit including the following acts. A plurality of transistors are formed. At least one dielectric layer is formed on or above the transistors. A plurality of connecting structures are formed in the dielectric layer. The connecting structures are respectively and electrically connected to the transistors. A plurality of separated conductive wells are respectively formed in electrical contact with the connecting structures.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: October 27, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzo-Hung Luo, Chin-Hung Chiang
  • Publication number: 20150221689
    Abstract: Embodiments of mechanisms for forming an image sensor device structure are provided. The image sensor device structure includes a substrate and a transfer transistor formed on the substrate. The image sensor device structure also includes a floating node formed in the substrate and a photosensitive element formed in the substrate. The transfer transistor is formed between the floating node and the photosensitive element, and the photosensitive element includes a first doping region with a lateral doping gradient.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yueh-Chuan LEE, Tzo-Hung LUO
  • Publication number: 20150200215
    Abstract: A manufacturing method of a sensing integrated circuit including the following acts. A plurality of transistors are formed. At least one dielectric layer is formed on or above the transistors. A plurality of connecting structures are formed in the dielectric layer. The connecting structures are respectively and electrically connected to the transistors. A plurality of separated conductive wells are respectively formed in electrical contact with the connecting structures.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
    Inventors: Tzo-Hung Luo, Chin-Hung Chiang
  • Patent number: 7378744
    Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: May 27, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Shin Tsai, Yu-Hua Chou, Tzo-Hung Luo, Chi-Chan Tseng, Wei Zhang, Jong-Chen Yang
  • Patent number: 7358612
    Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: April 15, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jian-Shin Tsai, Yu-Hua Chou, Tzo-Hung Luo, Chi-Chan Tseng, Wei Zhang, Jong-Chen Yang
  • Publication number: 20070010080
    Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.
    Type: Application
    Filed: May 22, 2006
    Publication date: January 11, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Shin Tsai, Yu-Hua Chou, Tzo-Hung Luo, Chi-Chan Tseng, Wei Zhang, Jong-Chen Yang
  • Publication number: 20060216916
    Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.
    Type: Application
    Filed: May 22, 2006
    Publication date: September 28, 2006
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Shin Tsai, Yu-Hua Chou, Tzo-Hung Luo, Chi-Chan Tseng, Wei Zhang, Jong-Chen Yang
  • Patent number: 7067409
    Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: June 27, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian Shin Tsai, Yu Hua Chou, Tzo Hung Luo, Chi Chan Tseng, Wei Zhang, Jong Chen Yang
  • Publication number: 20050250320
    Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.
    Type: Application
    Filed: May 10, 2004
    Publication date: November 10, 2005
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Jian Tsai, Yu-Hua Chou, Tzo-Hung Luo, Chi-Chan Tseng, Wei Zhang, Jong-Chen Yang