Abstract: A substrate strip with warpage-preventive linkage structure is proposed for a BGA (Ball Grid Array) application. The proposed substrate strip is composed of a series of substrates, each being used for the construction of an individual unit of a BGA package, and which is characterized by the provision of a warpage-preventive linkage structure, by which each substrate on the substrate strip is supported by means of no more than two tie bars, i.e., either by a two-point linkage structure or a one-point linkage structure, in contrast to the four-point linkage structure utilized by the prior art. During high-temperature fabrication steps when the substrate is subjected to thermal stresses, the substrate can freely expand toward the corners where no tie bars are provided; and consequently, it can be unwarped by the thermal stresses. This unwarped substrate allows the subsequently implanted ball grid array thereon to have high coplanarity.

Abstract: A semiconductor package with a heat sink is proposed, in which a chip has its first surface attached to a chip carrier, while a second surface of the chip is attached to a heat sink through an adhesive, allowing heat generated by the chip to be transmitted to the heat sink. Moreover, in a molding process, a molding resin is used to form an encapsulant for encapsulating the chip, while a top surface and side surfaces connected to the top surface of the heat sink are exposed to outside of the encapsulant, that is, the heat sink merely has its bottom surface bonded to the encapsulant. This makes the generated heat directly dissipated to the atmosphere through the heat sink. Furthermore, the top surface of the heat sink is coated with an interface layer, while adhesion between the interface layer and the molding resin is smaller than that between the heat sink and the encapsulant.

Abstract: A semiconductor package with a heat sink is proposed, in which a chip has its first surface attached to a chip carrier, while a second surface of the chip is attached to a heat sink through an adhesive, allowing heat generated by the chip to be transmitted to the heat sink. Moreover, in a molding process, a molding resin is used to form an encapsulant for encapsulating the chip, while a top surface and side surfaces connected to the top surface of the heat sink are exposed to outside of the encapsulant, that is, the heat sink merely has its bottom surface bonded to the encapsulant. This makes the generated heat directly dissipated to the atmosphere through the heat sink. Furthermore, the top surface of the heat sink is coated with an interface layer, while adhesion between the interface layer and the molding resin is smaller than that between the heat sink and the encapsulant.

Abstract: A semiconductor package and a method for fabricating the same are proposed, wherein, in a molding process for encapsulating a semiconductor chip mounted on a substrate, a mold is used with a molding cavity formed with a plurality of recess portions relatively smaller in height, and with a plurality of air vents for connecting the recess portions to outside of the mold and for ventilate air in the molding cavity. This allows a molding resin used during molding to slow down its flow when flowing into the recess portions, as the molding resin rapidly absorbs heat transmitted from the mold and is increased in viscosity thereof. The slowed down molding resin can therefore be prevented from flashing out of the air vents, so that quality and appearance of the fabricated semiconductor package can be well assured.

Abstract: A semiconductor package with a heat sink is proposed, in which a chip has its first surface attached to a chip carrier, while a second surface of the chip is attached to a heat sink through an adhesive, allowing heat generated by the chip to be transmitted to the heat sink. Moreover, in a molding process, a molding resin is used to form an encapsulant for encapsulating the chip, while a top surface and side surfaces connected to the top surface of the heat sink are exposed to outside of the encapsulant, that is, the heat sink merely has its bottom surface bonded to the encapsulant. This makes the generated heat directly dissipated to the atmosphere through the heat sink. Furthermore, the top surface of the heat sink is coated with an interface layer, while adhesion between the interface layer and the molding resin is smaller than that between the heat sink and the encapsulant.

Abstract: A thermally-enhanced wafer-level chip scale package (WLCSP) and method of fabricating the same is proposed, which allows easy integration of a thermally-conductive stiffener to each package unit fabricated through the WLCSP technology. The proposed WLCSP technology is characterized by the attachment of a thermally-conductive stiffener to the back side of the semiconductor wafer, which is subsequently cut during the singulation process into separate pieces respectively attached on each of the singulated integrated circuit chips from the semiconductor wafer. The thermally-conductive stiffener riot only serves as a heat-dissipation means for each chip during operation, but also serves to reinforce the chip so that the chip can be protected against cracking or chipping during flip-chip die bonding process or during handling and transportation.

Abstract: A semiconductor package with a crack-preventing member is proposed, in which a chip is mounted on a chip carrier by means of an adhesive and is electrically connected to the chip carrier. The crack-preventing member is formed at a proper position on the chip, and generates compression stress on the chip to sufficiently counteract tension stress produced from the chip carrier and adhesive in a molding process. This can effectively prevent the chip from cracking during molding, and thus improve the quality of fabricated products.

Abstract: A QFN (Quad Flat Non-leaded) semiconductor packaging technology is proposed, which can be used to package a semiconductor chip of a central-pad type having at least one row of bond pads arranged along a center line on one surface of the semiconductor chip. The proposed semiconductor packaging technology is based on a specially-designed leadframe which is formed with a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus for the packaged chip, and the ground wing is electrically linked to the chip-support-and-grounding structure. After encapsulation process is completed, the ground wing as well as the outer lead portions are exposed to the bottom outside of the encapsulation body, which can be then bonded a PCB's ground plane during SMT (Surface Mount Technology) process, thus enhancing the grounding effect and the electrical performance of the packaged chip during operation.

Abstract: A fabricating method for a semiconductor package is proposed, in which a chip carrier accommodates at least one semiconductor chip, which is attached with an interface layer formed on a covering module plate consisting of at least one covering plate, while the interface layer is poor in adhesion to the chip and a molding compound used for forming an encapsulant. So that after completing molding, ball implantation and singulation processes, the interface layer, the covering plate and a portion of the encapsulant formed on the covering plate can be easily removed by heating the singulated semiconductor package. This allows the molding compound not to flash on the chip, and prevents the chip from being damaged by stress generated in the molding process.

Abstract: A semiconductor package is proposed, in which at least one chip is mounted on a substrate, and at least one die-attach region is formed on the substrate. A plurality of thermal vias formed in the die-attach region and penetrating the substrate, in a manner that the thermal vias each has a top end connected to the chip mounted on the substrate and a bottom end connected to a thermal pad formed beneath the substrate at a position corresponding to the die-attach region. The thermal pad has a surface directly exposed to the atmosphere, allowing heat generated by the chip to be dissipated through the thermal vias and the exposed surface of the thermal pad to the atmosphere, so as to significantly improve heat dissipating efficiency for the semiconductor package.

Abstract: A semiconductor package with stacked chips is proposed, in which a first chip mounted on and electrically connected to a chip carrier is attached with a rigid interposer thereto, while the rigid interposer has a second chip disposed thereon in a manner that the rigid interposer is interposed between the first chip and the second chip. With the use of the rigid interposer, the second chip stacked on the first chip can be positioned in planarly parallel to the chip carrier, allowing bonding wires for electrically connecting the second chip to the chip carrier to be bonded completely. Moreover, the second chip has portions thereof not located right above the first chip to be firmly supported by the rigid interposer, and thus the second chip can be prevented from cracking in the wire bonding process.

Abstract: A stacked multi-chip package structure with on-chip integration of passive component is proposed, which is characterized in the mounting of passive component on a remaining surface area of the underlying semiconductor chip that is unoccupied by the overlying semiconductor chip, so that the overall package construction can be made more compact in size. The proposed package structure comprises: a substrate; a first semiconductor chip mounted over the substrate; a second semiconductor chip mounted over the first semiconductor chip; and at least one passive component mounted beside the second semiconductor chip and over the first semiconductor chip. The first and second semiconductor chips can be mounted by means of adhesive layers or flip chip technology. The passive component can be electrically coupled to the semiconductor chips through the use of wire-bonding technology (WBT) or surface-mount technology (SMT).

Abstract: A semiconductor package with a crack-preventing member is proposed, in which a chip is mounted on a chip carrier by means of an adhesive and is electrically connected to the chip carrier. The crack-preventing member is formed at a proper position on the chip, and generates compression stress on the chip to sufficiently counteract tension stress produced from the chip carrier and adhesive in a molding process. This can effectively prevent the chip from cracking during molding, and thus improve the quality of fabricated products.

Abstract: A semiconductor package with stacked chips is proposed, wherein at least two chips are stacked on a chip carrier in a stagger manner as to dispose a second chip on a first chip, and a supporting element is disposed on the second chip and dimensioned to cover area on the second chip with no support from the first chip. The supporting element provides support to the second chip, allowing bonding wires to be successfully connected to the second chip, without the occurrence of cracks of the second chip. The supporting element can be formed on its lower surface with protruding portions positioned outside edge sides of the second chip; this is to enhance structural strength of the supporting element, and help maintain the second chip intact in structure during wire bonding. The supporting element can further have its upper surface to be exposed to the atmosphere; this improves heat dissipating efficiency of the semiconductor package.

Abstract: A semiconductor package is proposed, in which at least one chip is mounted on a substrate, and at least one die-attach region is formed on the substrate. A plurality of thermal vias formed in the die-attach region and penetrating the substrate, in a manner that the thermal vias each has a top end connected to the chip mounted on the substrate and a bottom end connected to a thermal pad formed beneath the substrate at a position corresponding to the die-attach region. The thermal pad has a surface directly exposed to the atmosphere, allowing heat generated by the chip to be dissipated through the thermal vias and the exposed surface of the thermal pad to the atmosphere, so as to significantly improve heat dissipating efficiency for the semiconductor package.

Abstract: A QFN (Quad Flat Non-leaded) semiconductor packaging technology is proposed, which can be used to package a semiconductor chip of a central-pad type having at least one row of bond pads arranged along a center line on one surface of the semiconductor chip. The proposed semiconductor packaging technology is based on a specially-designed leadframe which is formed with a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus for the packaged chip, and the ground wing is electrically linked to the chip-support-and-grounding structure. After encapsulation process is completed, the ground wing as well as the outer lead portions are exposed to the bottom outside of the encapsulation body, which can be then bonded a PCB's ground plane during SMT (Surface Mount Technology) process, thus enhancing the grounding effect and the electrical performance of the packaged chip during operation.

Abstract: A semiconductor package with an embedded heat-dissipating device is proposed. The heat-dissipating device including a heat sink and a plurality of connecting bumps attached to connecting pads formed on the heat sink is mounted on a substrate by reflowing the connecting bumps to ball pads of the substrate. The connecting bumps and the ball pads help buffer a clamping force generated during the molding process, so as to prevent a packaged semiconductor chip from being cracked. Moreover, the reflowing process allows the connecting bumps to be self-aligned on the substrate, so as to assure the toning and planarity of the heat sink mounted thereon. Accordingly, during molding, the precisely-positioned beat sink can have its upper side closely abutting an upper mold, allowing a molding resin to be prevented from flashing on the upper side thereof i.e.

Abstract: A semiconductor package with a heat sink is proposed, in which a chip has its first surface attached to a chip carrier, while a second surface of the chip is attached to a heat sink through an adhesive, allowing heat generated by the chip to be transmitted to the heat sink. Moreover, in a molding process, a molding resin is used to form an encapsulant for encapsulating the chip, while a top surface and side surfaces connected to the top surface of the heat sink are exposed to outside of the encapsulant, that is, the heat sink merely has its bottom surface bonded to the encapsulant. This makes the generated heat directly dissipated to the atmosphere through the heat sink. Furthermore, the top surface of the heat sink is coated with an interface layer, while adhesion between the interface layer and the molding resin is smaller than that between the heat sink and the encapsulant.

Abstract: A semiconductor package and a method for fabricating the same are proposed, wherein, in a molding process for encapsulating a semiconductor chip mounted on a substrate, a mold is used with a molding cavity formed with a plurality of recess portions relatively smaller in height, and with a plurality of air vents for connecting the recess portions to outside of the mold and for ventilate air in the molding cavity. This allows a molding resin used during molding to slow down its flow when flowing into the recess portions, as the molding resin rapidly absorbs heat transmitted from the mold and is increased in viscosity thereof. The slowed down molding resin can therefore be prevented from flashing out of the air vents, so that quality and appearance of the fabricated semiconductor package can be well assured.

Abstract: A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the chips, with an interface layer formed on a top surface of the heat spreader module plate. The chip carrier module plate, the chips and the heat spreader module plate are encapsulated. Adhesion force between the interface layer and the encapsulant is larger than that between the interface layer and the heat spreader module plate, and adhesion force between the interface layer and the heat spreader module plate is smaller than that between the heat spreader module plate and the encapsulant.