Abstract: A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.

Abstract: A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.

Abstract: A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.

Abstract: A circuit is powered through a P-type transistor whose thermal instability behavior is to be evaluated. The threshold of the P-type transistor under evaluation and consequently the saturation current of the transistor are reflected in the frequency of the circuit, which in one embodiment is a ring oscillator. Additional circuitry is connected to the P-type transistor and the ring oscillator to ensure the proper stress conditions for the transistor and consequently to the evaluation of the P-type transistor.

Abstract: A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.

Abstract: A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.

Abstract: A sensor circuit is used to provide bit-cell read strength distribution of an SRAM array. A current-mirror circuit mirroring the bit-line current of an SRAM array is used to power the sensor circuit. A reference current representing nominal bit-cell read current is used as a reference. The current-mirror circuit senses the bit-line current. The current-mirror and the ring oscillator are not part of the bit-line read path.

Abstract: A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.

Abstract: A sensor circuit is used to provide bit-cell read strength distribution of an SRAM array. A current-mirror circuit mirroring the bit-line current of an SRAM array is used to power the sensor circuit. A reference current representing nominal bit-cell read current is used as a reference. The current-mirror circuit senses the bit-line current. The current-mirror and the ring oscillator are not part of the bit-line read path.

Abstract: A circuit is powered through a P-type transistor whose thermal instability behavior is to be evaluated. The threshold of the P-type transistor under evaluation and consequently the saturation current of the transistor are reflected in the frequency of the circuit, which in one embodiment is a ring oscillator. Additional circuitry is connected to the P-type transistor and the ring oscillator to ensure the proper stress conditions for the transistor and consequently to the evaluation of the P-type transistor.

Abstract: In one embodiment, one portion of an SRAM array is stressed by first writing a “1” in every bit of the array, followed by an evaluation of the relevant parameters of the array using a ring oscillator driven by a mirrored bit-line current, the ring oscillator not in line of the bit-line of the SRAM. The other portion of the array is then stressed after writing a “0” in every bit of the array. The evaluation procedure is then repeated.

Abstract: Systems and methods are disclosed for managing power consumption in electronic devices. In certain embodiments, an integrated circuit for managing power consumption in an electronic device includes an input/output (I/O) interface, a first circuit block coupled to the I/O interface, and an interface circuit coupled between the I/O interface and the first circuit block, the interface circuit configured to provide a defined logic state to the first circuit block or a second circuit block external to the integrated circuit if one of the first circuit block or the second circuit block is powered down. By providing a defined logic state to the first circuit block or the second circuit block when one of the first circuit block or the second circuit block is powered down, power consumption of the electronic device may be reduced.

Abstract: A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode.

Abstract: Systems and methods are disclosed for managing power consumption in electronic devices. In certain embodiments, an integrated circuit for managing power consumption in an electronic device includes an input/output (I/O) interface, a first circuit block coupled to the I/O interface, and an interface circuit coupled between the I/O interface and the first circuit block, the interface circuit configured to provide a defined logic state to the first circuit block or a second circuit block external to the integrated circuit if one of the first circuit block or the second circuit block is powered down. By providing a defined logic state to the first circuit block or the second circuit block when one of the first circuit block or the second circuit block is powered down, power consumption of the electronic device may be reduced.

Abstract: A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode.

Abstract: Capacitive coupling correction circuits are coupled between adjacent parallel dynamic (pre-charged) or static conductors. The capacitive coupling correction circuits effectively isolate a low voltage applied to a first conductor from a high pre-charged voltage stored on an adjacent second conductor (or vice versa). The adjacent parallel conductors can be bit lines of a memory cell. Each capacitive coupling correction circuit can include an inverter having an input terminal coupled to the first conductor, and an output terminal coupled to a first plate of a capacitor. A second plate of the capacitor is coupled to the second conductor. The capacitance of the capacitor is selected to be identical to a parasitic capacitance between the first and second conductors. As a result, there is a zero net voltage effect between the first and second conductors. The capacitive coupling correction circuits may be distributed along the length of the first and second conductors.

Abstract: A collision detection circuit for a multi-port memory system is presented. The collision detection circuit detects a collision condition if the addresses at two or more ports at the same time match and if one of the two or more ports is writing to the memory location associated with that address. A collision flag can then be set when the collision condition exists. In some embodiments, arbitration can occur when the collision flag is set.

Abstract: A six transistor content addressable memory (CAM) cell that prevents disturb of non-written rows during a write operation. The CAM cell comprises an SRAM cell having a pair of cross-coupled inverters and a pair of access transistors. The SRAM cell stores a data value at the output node of one of the inverters and an inverse data value at the output node of the other one of the inverters. An access transistor is connected between each output node and a match line. The match line is connected across the access transistors such that the match line is coupled to the output nodes of the inverters when the access transistors are turned on. Data lines are connected to the gates of the access transistors, and are coupled to receive a data value and an inverse data value. The 6-T CAM cell of this embodiment can be coupled to a plurality of identical 6-T CAM cells to form an array. Each row of CAM cells is coupled to the same match line.