Patents by Inventor Tzu-Ang Chiang

Tzu-Ang Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11398391
    Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a plurality of holding members and at least a first injector. The plurality of holding members are configured to hold a substrate. The substrate includes a front surface and a back surface opposite to the front surface. The first injector is below the holding members and is configured to face the back surface of the substrate. The first injector is displaced from a projection of a center of the substrate from a top view perspective. A method for processing a substrate is also provided.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Po-Yuan Wang, Tzu Ang Chiang, Jian-Jou Lian, Yu Shih Wang, Chun-Neng Lin, Ming-Hsi Yeh
  • Publication number: 20220189776
    Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Jian-Jou Lian, Po-Yuan Wang, Chieh-Wei Chen
  • Publication number: 20220140107
    Abstract: A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Inventors: Jian-Jou Lian, Chun-Neng LIN, Ming-Hsi YEH, Chieh-Wei CHEN, Tzu-Ang CHIANG
  • Patent number: 11309185
    Abstract: A method includes forming a gate trench over a semiconductor fin. The gate trench includes an upper portion surrounded by first gate spacers and a lower portion surrounded by second gate spacers and the first gate spacers. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is disposed over a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate electrode overlaying the metal gate in the lower portion of the gate trench, while keeping sidewalls of the first gate spacers and upper surfaces of the second gate spacer overlaid by a second portion of the gate dielectric layer. The method includes removing the second portion of the gate dielectric layer, while remaining the gate electrode substantially intact.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Jian-Jou Lian, Po-Yuan Wang, Chieh-Wei Chen
  • Patent number: 11309190
    Abstract: In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Chieh-Wei Chen, Tzu-Ang Chiang, Ming-Hsi Yeh
  • Publication number: 20220115519
    Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Inventors: Jian-Jou Lian, Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Po-Yuan Wang, Chieh-Wei Chen
  • Patent number: 11227940
    Abstract: A method of forming a semiconductor device includes removing a dummy gate from over a semiconductor fin; depositing a glue layer and a fill metal over the semiconductor fin; and simultaneously etching the glue layer and the fill metal with a wet etching solution, the wet etching solution etching the glue layer at a faster rate than the fill metal and reshaping the fill metal.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Ming-Hsi Yeh, Chieh-Wei Chen, Tzu-Ang Chiang
  • Publication number: 20220013412
    Abstract: A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 13, 2022
    Inventors: Chieh-Wei Chen, Jian-Jou Lian, Tzu-Ang Chiang, Chun-Neng Lin, Ming-Hsi Yeh
  • Patent number: 11201084
    Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin protruding above a substrate, where the first dummy gate structure and the second dummy gate structure are surrounded by a dielectric layer; and replacing the first dummy gate structure and the second dummy gate structure with a first metal gate and a second metal gate, respectively, where the replacing includes: removing the first and the second dummy gate structures to form a first recess and a second recess in the dielectric layer, respectively; forming a gate dielectric layer in the first recess and in the second recess; forming an N-type work function layer and a capping layer successively over the gate dielectric layer in the second recess but not in the first recess; and filling the first recess and the second recess with an electrically conductive material.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Chieh-Wei Chen, Jian-Jou Lian, Chun-Neng Lin, Tzu-Ang Chiang, Ming-Hsi Yeh
  • Publication number: 20210366737
    Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a plurality of holding members and at least a first injector. The plurality of holding members are configured to hold a substrate. The substrate includes a front surface and a back surface opposite to the front surface. The first injector is below the holding members and is configured to face the back surface of the substrate. The first injector is displaced from a projection of a center of the substrate from a top view perspective. A method for processing a substrate is also provided.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Inventors: PO-YUAN WANG, TZU ANG CHIANG, JIAN-JOU LIAN, YU SHIH WANG, CHUN-NENG LIN, MING-HSI YEH
  • Publication number: 20210335613
    Abstract: A method includes forming a gate trench over a semiconductor fin. The gate trench includes an upper portion surrounded by first gate spacers and a lower portion surrounded by second gate spacers and the first gate spacers. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is disposed over a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate electrode overlaying the metal gate in the lower portion of the gate trench, while keeping sidewalls of the first gate spacers and upper surfaces of the second gate spacer overlaid by a second portion of the gate dielectric layer. The method includes removing the second portion of the gate dielectric layer, while remaining the gate electrode substantially intact.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 28, 2021
    Inventors: Tzu Ang CHIANG, Ming-Hsi Yeh, Chun-Neng Lin, Jian-Jou Lian, Po-Yuan Wang, Chieh-Wei CHEN
  • Publication number: 20210273073
    Abstract: A method of forming a semiconductor device includes removing a dummy gate from over a semiconductor fin; depositing a glue layer and a fill metal over the semiconductor fin; and simultaneously etching the glue layer and the fill metal with a wet etching solution, the wet etching solution etching the glue layer at a faster rate than the fill metal and reshaping the fill metal.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Ming-Hsi Yeh, Chieh-Wei Chen, Tzu-Ang Chiang
  • Publication number: 20210225660
    Abstract: In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Chieh-Wei Chen, Tzu-Ang Chiang, Ming-Hsi Yeh
  • Publication number: 20210119034
    Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Chieh-Wei Chen, Tzu-Ang Chiang, Ming-Hsi Yeh
  • Publication number: 20210057282
    Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin protruding above a substrate, where the first dummy gate structure and the second dummy gate structure are surrounded by a dielectric layer; and replacing the first dummy gate structure and the second dummy gate structure with a first metal gate and a second metal gate, respectively, where the replacing includes: removing the first and the second dummy gate structures to form a first recess and a second recess in the dielectric layer, respectively; forming a gate dielectric layer in the first recess and in the second recess; forming an N-type work function layer and a capping layer successively over the gate dielectric layer in the second recess but not in the first recess; and filling the first recess and the second recess with an electrically conductive material.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Chieh-Wei Chen, Jian-Jou Lian, Chun-Neng Lin, Tzu-Ang Chiang, Ming-Hsi Yeh