Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.

Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.

Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.

Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.

Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.

Abstract: A frequency tripler includes a double-frequency in-phase signal generator, a double-frequency quadrature signal generator and a mixer. The double-frequency in-phase signal generator is arranged for receiving at least an in-phase signal and a quadrature signal to generate a double-frequency in-phase signal whose frequency is twice that of the in-phase signal or the quadrature signal; the double-frequency quadrature signal generator is arranged for receiving at least the in-phase signal and the quadrature signal to generate a double-frequency quadrature signal whose frequency is twice that of the in-phase signal or the quadrature signal; and the mixer is arranged for receiving the in-phase signal, the quadrature signal, the double-frequency in-phase signal and the double-frequency quadrature signal to generate an output signal whose frequency is triple that of the in-phase signal or the quadrature signal.

Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.

Abstract: A frequency tripler includes a double-frequency in-phase signal generator, a double-frequency quadrature signal generator and a mixer. The double-frequency in-phase signal generator is arranged for receiving at least an in-phase signal and a quadrature signal to generate a double-frequency in-phase signal whose frequency is twice that of the in-phase signal or the quadrature signal; the double-frequency quadrature signal generator is arranged for receiving at least the in-phase signal and the quadrature signal to generate a double-frequency quadrature signal whose frequency is twice that of the in-phase signal or the quadrature signal; and the mixer is arranged for receiving the in-phase signal, the quadrature signal, the double-frequency in-phase signal and the double-frequency quadrature signal to generate an output signal whose frequency is triple that of the in-phase signal or the quadrature signal.

Abstract: A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.

Abstract: A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell.

Abstract: A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell.

Abstract: A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.