Abstract: An immersion cooling equipment is configured to cool an electronic device. The immersion cooling equipment includes a tank and a hollow fluid blocking member. The tank is filled with coolant. The electronic device is disposed in the tank and immersed in the coolant. The hollow fluid blocking member is replaceably placed in the tank to be immersed in the coolant. During a process of placing the hollow fluid blocking member into the tank, a portion of the coolant in the tank flows into the hollow fluid blocking member, and during a process of detaching the hollow fluid blocking member from the tank, the coolant in the hollow fluid blocking member flows out of the hollow fluid blocking member and flows back to the tank.

Abstract: Discussed is a battery module, which includes a plurality of battery assemblies and a flexible rod. Each battery assembly includes a frame and at least one battery unit, and the at least one battery unit is disposed within the frame. The flexible rod sequentially passes through the plurality of battery assemblies, and the plurality of battery assemblies jointly construct a structure configured to be curved by bending the flexible rod.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate and at least one contact plug. The substrate has an epi-layer. The contact plug is formed on the epi-layer and includes a silicide cap disposed on the epi-layer; a conductive pillar disposed on the silicide cap such that the conductive pillar electrically connects to the epi-layer via the silicide cap; and a hybrid liner. The hybrid liner surrounds the conductive pillar and includes a lower portion abutting the silicide cap and having a nitride material and an upper portion abutting the conductive pillar and having an oxidized nitride material. Due to the hybrid liner, a semiconductor structure with increased capacitance and decreased resistivity can be obtained.

Abstract: A light-emitting device array includes a first light-emitting device, a second light-emitting device, and a third light-emitting device. A first beam shaping structure of the first light-emitting device is configured to convert light emitted by a first light-emitting structure of first light-emitting device into first structured light. A second beam shaping structure of the second light-emitting device is configured to convert light emitted by a second light-emitting structure of second light-emitting device into second structured light. Speckle patterns and spatial distributions of the first structured light and the second structured light on a projection plane are the same. A third beam shaping structure of the third light-emitting device is configured to convert light emitted by a third light-emitting structure of third light-emitting device into third structured light.

Abstract: A sheet detection device includes: a magnetic sensing element disposed on a sheet guide, wherein the sheet guide brings the magnetic sensing element to move to a first position or a second position; a first magnetic element disposed on a sheet tray corresponding to the first position; a second magnetic element disposed on the sheet tray corresponding to the second position and in spaced with the first magnetic element; a processing element electrically connected with the magnetic sensing element. When the magnetic sensing element outputs a first voltage signal, the processing element determines the sheet guide is located at the first position according to the first voltage signal. When the magnetic sensing element outputs a second voltage signal, the processing element determines the sheet guide is located at the second position according to the second voltage signal. The first voltage signal is different from the second voltage signal.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

Abstract: A package structure includes a first bonding film on a first package component and a first alignment mark in the first bonding film. The first alignment mark includes a plurality of first patterns spaced apart from each other. The package structure includes a second bonding film on a second package component and bonded to the first bonding film, and a second alignment mark in the second bonding film. The second alignment mark includes a plurality of second patterns spaced apart from each other, and the first patterns overlap the second patterns. In this case, an interference pattern can be formed by the optical signal passing through the varying spacing between the gratings of top wafer and bottom wafer due to pitch difference between first pitch and second pitch. By reading the optical signal, the resolution of overlay (misalignment) measurement is improved.

Abstract: A medical image processing method includes obtaining a first set of projection data by performing, with a first CT apparatus including a first detector with a first pixel size, a first CT scan of an object in a first imaging region of the first detector; obtaining a first CT image with a first resolution by reconstructing the first set of projection data; obtaining a processed CT image with a resolution higher than the first resolution by applying a machine-learning model for resolution enhancement to the first CT image; and displaying the processed CT image or outputting the processed CT image for analysis. The machine-learning model is obtained by training using a second CT image based on a second set of projection data acquired by a second CT scan of the object in a second imaging region with a second CT apparatus including a second detector with a second pixel size.

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.

Abstract: In some embodiments, the present disclosure relates to an image sensor including a substrate having a first side and a second side opposite the first side; a photodetector region within the substrate; a gate structure on the first side of the substrate over the photodetector region; a deep trench isolation (DTI) structure surrounding the photodetector region and extending from the first side of the substrate to the second side; a doped floating node region within the substrate at the first side and disposed between the gate structure and the DTI structure; and a floating node on the first side of the substrate, contacting a top surface of the DTI structure and overlying the doped floating node region.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: A slide rail assembly includes a first rail, a second rail, a slide assisting device, an elastic member and a working member. The second rail and the first rail are movable relative to each other. The elastic member is arranged on the second rail. During a process of the second rail being moved relative to the first rail along an opening direction, the working member is configured to contact the elastic member in an initial state in order to drive the slide assisting device to move along the opening direction to a predetermined position. When the slide assisting device is located at the predetermined position, the elastic member releases an elastic force through a predetermined space of the first rail, such that the elastic member is no longer in the initial state with the working member no longer contacting the elastic member.

Abstract: A detecting method of a sheet detection device includes: generating, by a first magnetic sensing element, a first voltage signal corresponding to a magnetic element; generating, by a second magnetic sensing element, a second voltage signal corresponding to the magnetic element; determining, by a processing element, a first relative position of the magnetic element relative to the first magnetic sensing element according to the first voltage signal; determining, by the processing element, a second relative position of the magnetic element relative to the second magnetic sensing element according to the second voltage signal; determining, by the processing element, a stopping position of the magnetic element according to the first relative position and the second relative position; determining, by the processing element, a paper size of a paper abutted by a paper guide according to the stopping position. A sheet detection device is also disclosed.

Abstract: A method of maximizing power efficiency for a power amplifier system comprises obtaining a power supply voltage; determining a first voltage level sufficient for a power amplifier of the power amplifier system to output an output power; determining a second voltage level lower than the first voltage level; determining whether the power amplifier is activated, to generate a determination result; determining to convert the power supply voltage into a supply voltage with the first voltage level or the second voltage level according to the determination result; and supplying the power amplifier with the supply voltage.

Abstract: A semiconductor structure is provided in the present invention, including a substrate, a deep N-well formed in the substrate, a first well formed in the deep N-well, a first gate formed on the first well, a first source and a first drain formed respectively at two sides of the first gate in the first well, a first doped region formed in the first well, and a metal interconnect electrically connected with the first source and the first doped region, wherein an area of the deep N-well multiplied by a first parameter is a first factor, an area of the first gate multiplied by a second parameter is a second factor, and an area of the metal interconnect divided by a sum of the first factor and the second factor is less than a specification value.

Abstract: The present disclosure relates to an anti-glucose-regulated protein 78 (GRP78) antibody or an antigen-binding fragment thereof. The present disclosure also relates to a method for treating and/or preventing a disease and/or disorder caused by or related to GRP78 activity or signaling, and a method or kit for detecting GRP78 or a cancer in a sample.

Abstract: An integrated circuit (IC) with conductive structures and a method of fabricating the IC are disclosed. The method includes depositing a first dielectric layer on a semiconductor device, forming a conductive structure in the first dielectric layer, removing a portion of the first dielectric layer to expose a sidewall of the conductive structure, forming a barrier structure surrounding the sidewall of the conductive structure, depositing a conductive layer on the barrier structure, and performing a polishing process on the barrier structure and the conductive layer.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.