Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.

Abstract: A package structure includes a first bonding film on a first package component and a first alignment mark in the first bonding film. The first alignment mark includes a plurality of first patterns spaced apart from each other. The package structure includes a second bonding film on a second package component and bonded to the first bonding film, and a second alignment mark in the second bonding film. The second alignment mark includes a plurality of second patterns spaced apart from each other, and the first patterns overlap the second patterns. In this case, an interference pattern can be formed by the optical signal passing through the varying spacing between the gratings of top wafer and bottom wafer due to pitch difference between first pitch and second pitch. By reading the optical signal, the resolution of overlay (misalignment) measurement is improved.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.

Abstract: A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.

Abstract: A method for forming a semiconductor device is provided. The method includes forming first bonding features and a first alignment mark including first patterns in a top die and forming second bonding features and a second alignment mark in a bottom wafer. The method also includes determining a first benchmark and a second benchmark. The method further includes aligning the top die with the bottom wafer using the first alignment mark and the second alignment mark. In a top view, at least two of the first patterns are oriented along a first direction, and at least two of the first patterns are oriented along a second direction that is different from the first direction. The top die is aligned with the bottom wafer by adjusting a virtual axis passing through the first benchmark and the second benchmark to be substantially parallel with the first direction.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.

Abstract: A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.

Abstract: A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.

Abstract: A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: A system and method is disclosed for a quality control and/or inspection procedure for assembly line processes. The disclosed system and method enable automatic optical inspection of a device during different stages of manufacture as well as in its finished form. The disclosed system and method enable the automatic quality control process to be self-learning, dynamic, and to identify and classify defects in real time.

Abstract: A heating and heat dissipating multi-layer circuit board structure for keeping operating temperatures of electronic components is provided. The outer layer of the multi-layer printed circuit board is in contact with electronic components. The operating temperatures of electronic components are measured through by a temperature measuring circuit. When the operating temperature of at least one electronic component is lower than a default temperature, the heating circuits corresponding to the electronic components are enabled respectively to heat the electronic components through corresponding heat conduction elements. When the operating temperature of at least one electronic component is higher than another default temperature, the heating circuits corresponding to the electronic components are disabled to transfer the heat from the electronic components to the heat conduction elements automatically.

Abstract: This specification discloses a device of controlling temperature gain and the method thereof. The invention detects the temperature of work environment and uses it to generate a control signal and a PWM signal for dynamically controlling the heaters around electronic elements to heat up. When the temperature of work environment is too low, the invention can increase the stability of the electronic elements.

Abstract: A heating and heat dissipating multi-layer circuit board structure for keeping operating temperatures of electronic components is provided. The outer layer of the multi-layer printed circuit board is in contact with electronic components. The operating temperatures of electronic components are measured through by a temperature measuring circuit. When the operating temperature of at least one electronic component is lower than a default temperature, the heating circuits corresponding to the electronic components are enabled respectively to heat the electronic components through corresponding heat conduction elements. When the operating temperature of at least one electronic component is higher than another default temperature, the heating circuits corresponding to the electronic components are disabled to transfer the heat from the electronic components to the heat conduction elements automatically.

Abstract: Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.