Abstract: A package comprises a substrate including a first surface, and an upper conductive layer arranged on the first surface, a first light-emitting unit arranged on the upper conductive layer, and comprises a first semiconductor layer, a first substrate, a first light-emitting surface and a first side wall, a second light-emitting unit, which is arranged on the upper conductive layer, and comprises a second light-emitting surface and a second side wall, a light-transmitting layer arranged on the first surface and covers the upper conductive layer, the first light-emitting unit, and the second light-emitting unit, a light-absorbing layer, which is arranged between the substrate and the light-transmitting layer in a continuous configuration of separating the first light-emitting unit and the second light-emitting unit from each other, and a reflective wall arranged on the first side wall, wherein a height of the reflective wall is lower than that of the light-absorbing layer.

Abstract: A high bandwidth, low latency middle-mile core communications network providing low-cost and high-speed communications among the users of the network. Embodiments of the invention include a number of network access points located at a number of spaced apart sites. At least some of these network access points in the network are in communication with each other via millimeter radio links with microwave backup links. In preferred embodiments the millimeter radio links include two millimeter radios, one transmitting in the frequency range of 71-76 GHz and receiving in the frequency range if 81 to 86 GHz and the other radio transmitting in the frequency range of 81-86 GHz and receiving in the frequency range if 71 to 76 GHz.

Abstract: A high bandwidth, low latency middle-mile core communications network providing low-cost and high-speed communications among the users of the network. Embodiments of the invention include a number of network access points located at a number of spaced apart sites. At least some of these network access points in the network are in communication with each other via millimeter radio links with microwave backup links. In preferred embodiments the millimeter radio links include two millimeter radios, one transmitting in the frequency range of 71-76 GHz and receiving in the frequency range if 81 to 86 GHz and the other radio transmitting in the frequency range of 81-86 GHz and receiving in the frequency range if 71 to 76 GHz. In these preferred embodiments each millimeter wave radio is equipped with an antenna designed to produce a millimeter wave beam with an angular spread of less than two degrees. A high-speed switch is located at each network access point.

Abstract: A high bandwidth, low latency middle-mile, last mile core communications network providing low-cost and high-speed communications among the users of the network. Embodiments of the invention include a number of network access points located at a number of spaced apart sites. At least some of these network access points in the network are in communication with each other via wireless radio links. The network provides backhaul communication between at least one communication switching center and a number of base stations.

Abstract: A method for wafer-to-wafer bonding of a sensor readout circuitry separately fabricated with a silicon substrate to a photodiode device made of non-silicon materials grown from a separate substrate. In preferred embodiments the non-silicon materials are epitaxially grown on a silicon wafer. The bonding technique of preferred embodiments of the present invention utilizes lithographically pre-fabricated metallic interconnects to connect each of a number of pixel circuits on a readout circuit wafer to each of a corresponding number of pixel photodiodes on a photodiode wafer. The metallic interconnects are extremely small (with widths of about 2 to 4 microns) compared to prior art bump bonds with the solder balls of diameter typically larger than 20 microns. The present invention also provides alignment techniques to assure proper alignment of the interconnects during the bonding step.

Abstract: A method for wafer-to-wafer bonding of a sensor readout circuitry separately fabricated with a silicon substrate to a photodiode device made of non-silicon materials grown from a separate substrate. In preferred embodiments the non-silicon materials are epitaxially grown on a silicon wafer. The bonding technique of preferred embodiments of the present invention utilizes lithographically pre-fabricated metallic interconnects to connect each of a number of pixel circuits on a readout circuit wafer to each of a corresponding number of pixel photodiodes on a photodiode wafer. The metallic interconnects are extremely small (with widths of about 2 to 4 microns) compared to prior art bump bonds with the solder balls of diameter typically larger than 20 microns. The present invention also provides alignment techniques to assure proper alignment of the interconnects during the bonding step.

Abstract: A MOS or CMOS based active pixel sensor with special sampling features to substantially eliminate clock noise. The sensor includes an array of pixels fabricated in or on a substrate, each pixel defining a charge collection node on which charges generated inside a photodiode region are collected, a charge integration node, at which charges generated in said pixel are integrated to produce pixel signals, a charge sensing node from which reset signals and the pixel signals are sensed. In preferred embodiments the sensor includes a continuous electromagnetic radiation detection structure located above the pixel circuits providing a photodiode region for each pixel. The sensor includes integrated circuit elements adapted to maintain voltage potentials of the charge integration nodes substantially constant during charge integration cycles. The sensor also includes integrated circuit elements having electrical capacitance adapted to store charges providing an electrical potential at the charge integration node.

Abstract: A hybrid MOS or CMOS image sensor. The sensor includes photon-sensing elements comprised of an array of photo-sensing regions deposited in the form of separate islands on or in a substrate. Pixel circuitry is created on and/or in the substrate at or near the edge of or beneath the photon-sensing elements. The photo-sensing elements may be comprised of multiple photo-sensing semiconductor layers or be created in a single photon-sensing semiconductor layer. Special circuitry is provided to keep the potential across the pixel photon-sensing element at or near zero volts to minimize or eliminate dark current. The potential difference is preferably less than 1.0 volt. The circuitry also keeps the small potential difference across the photodiodes constant or approximately constant throughout the charge collection cycle.

Abstract: A MOS or CMOS based active pixel sensor designed for operation with zero or close to zero potential across the pixel photodiodes to minimize or eliminate dark current. In this preferred embodiment, the voltage potential across the pixel photodiode structures is maintained constant and close to zero, preferably less than 1.0 volts. This preferred embodiment enables the photodiode to be operated at a constant bias condition during the charge detection cycle. In preferred embodiments the pixel photodiodes are produced with a continuous pin or nip photodiode layer laid down over pixel electrodes of the sensor. In other preferred embodiments the pixel photodiode structures are produced beside and physically isolated from the regions where CMOS circuits are formed. In some of these preferred embodiments the isolated pixel photodiode structures are comprised of crystalline germanium deposited in cavities in a silicon substrate. This embodiment can be adapted especially for imaging at short wave infrared frequencies.

Abstract: A MOS or CMOS based active pixel sensor designed for operation with zero or close to zero potential across the pixel photodiodes to minimize or eliminate dark current. In preferred embodiments the pixel photodiodes are produced with a continuous pin or nip photodiode layer laid down over pixel electrodes of the sensor. In this preferred embodiment, the voltage potential across the pixel photodiode structures is maintained constant and close to zero, preferably less than 1.0 volts. This preferred embodiment enables the photodiode to be operated at a constant bias condition during the charge detection cycle. Setting this constant bias condition close to zero (near “short circuit” condition) assures that dark current is substantially zero.

Abstract: A MOS or CMOS sensor for high performance imaging in broad spectral ranges including portions of the infrared spectral band. These broad spectral ranges may also include portions or all of the visible spectrum, therefore the sensor has both daylight and night vision capabilities. The sensor includes a continuous multi-layer photodiode structure on a many pixel MOS or CMOS readout array where the photodiode structure is chosen to include responses in the near infrared spectral ranges. A preferred embodiment incorporates a microcrystalline copper indium diselenide/cadmium sulfide photodiode structure on a CMOS readout array. An alternate preferred embodiment incorporates a microcrystalline silicon germanium photodiode structure on a CMOS readout array. Each of these embodiments provides night vision with image performance that greatly surpasses the GEN III night vision technology in terms of enhanced sensitivity, pixel size and pixel count.

Abstract: A monolithic ambient light detector. The detector includes on a single CMOS integrated circuit a photodiode matching almost perfectly the spectral response of the human eye and CMOS integrated circuitry for providing output digital signals indicating ambient light levels for controlling light intensity of electronic display monitors. The entire detector is fabricated on a single CMOS integrated circuit chip.

Abstract: An active pixel sensor for producing images from electron-hole producing radiation includes a crystalline semiconductor substrate having an array of electrically conductive diffusion regions, an interlayer dielectric (ILD) layer formed over the crystalline semiconductor substrate and comprising an array of contact electrodes, and an interconnect structure formed over the ILD layer, wherein the interconnect structure includes at least one layer comprising an array of conductive vias. An array of patterned metal pads is formed over the interconnect structure and are electrically connected to an array of charge collecting pixel electrodes. A radiation absorbing structure includes a photoconductive N-I-B-P photodiode layer formed over the interconnect structure, and a surface electrode layer establishes an electrical field across the radiation absorbing structure and between the surface electrode layer and each of the array of charge collecting pixel electrodes.

Abstract: A MOS or CMOS based active pixel sensor designed for operation with zero or close to zero potential across the pixel photodiodes to minimize or eliminate dark current. In preferred embodiments the pixel photodiodes are produced with a continuous pin or nip photodiode layer laid down over pixel electrodes of the sensor. In this preferred embodiment, the voltage potential across the pixel photodiode structures is maintained constant and close to zero, preferably less than 1.0 volts. This preferred embodiment enables the photodiode to be operated at a constant bias condition during the charge detection cycle. Setting this constant bias condition close to zero (near “short circuit” condition) assures that dark current is substantially zero.

Abstract: A MOS or CMOS based active pixel sensor with special sampling features to substantially eliminate clock noise. The sensor includes an array of pixels fabricated in or on a substrate, each pixel defining a charge collection node on which charges generated inside a photodiode region are collected, a charge integration node, at which charges generated in said pixel are integrated to produce pixel signals, a charge sensing node from which reset signals and the pixel signals are sensed. In preferred embodiments the sensor includes a continuous electromagnetic radiation detection structure located above the pixel circuits providing a photodiode region for each pixel. The sensor includes integrated circuit elements adapted to maintain voltage potentials of the charge integration nodes substantially constant during charge integration cycles. The sensor also includes integrated circuit elements having electrical capacitance adapted to store charges providing an electrical potential at the charge integration node.

Abstract: A MOS or CMOS sensor with a multi-layer photodiode layer covering an array of active pixel circuits. The multi-layer photodiode layer of each pixel is fabricated as continuous layers of charge generating material on top of the MOS and/or CMOS pixel circuits so that extremely small pixels are possible with almost 100 percent packing factors. The sensor includes special features to minimize or eliminate pixel to pixel crosstalk. A micro-lens array with a micro-lens positioned above each pixel directs light illuminating the pixel toward the central portion of the pixel and away from its edges. Also, preferably carbon is added to doped amorphous silicon N or P bottom layer of the multi-layer photodiode layer to increase the electrical resistivity in the bottom layer to further discourage crosstalk. In preferred embodiments each of the pixels define a tiny surface area equal to or larger than about 3.24 square microns and smaller than or equal to about 25 square microns.

Abstract: A MOS or CMOS sensor with a multi-layer photodiode layer covering an array of active pixel circuits. The multi-layer photodiode layer of each pixel is fabricated as continuous layers of charge generating material on top of the MOS and/or CMOS pixel circuits so that extremely small pixels are possible with almost 100 percent packing factors. The sensor includes special features to minimize or eliminate pixel to pixel crosstalk. A micro-lens array with a micro-lens positioned above each pixel directs light illuminating the pixel toward the central portion of the pixel and away from its edges. Also, preferably carbon is added to doped amorphous silicon N or P bottom layer of the multi-layer photodiode layer to increase the electrical resistivity in the bottom layer to further discourage crosstalk. In preferred embodiments each of the pixels define a tiny surface area equal to or larger than about 3.24 square microns and smaller than or equal to about 25 square microns.

Abstract: An electronic imaging sensor. The sensor includes an array of photo-sensing pixel elements for producing image frames. Each pixel element defines a photo-sensing region and includes a charge collecting element for collecting electrical charges produced in the photo-sensing region, and a charge storage element for the storage of the collected charges. The sensor also includes charge sensing elements for sensing the collected charges, and charge-to-signal conversion elements. The sensor also includes timing elements for controlling the pixel circuits to produce image frames at a predetermined normal frame rate based on a master clock signal (such as 12 MHz or 10 MHz). This predetermined normal frame rate which may be a video rate (such as about 30 frames per second or 25 frames per second) establishes a normal maximum per frame exposure time.

Abstract: A MOS or CMOS sensor for high performance imaging in broad spectral ranges including portions of the infrared spectral band. These broad spectral ranges may also include portions or all of the visible spectrum, therefore the sensor has both daylight and night vision capabilities. The sensor includes a continuous multi-layer photodiode structure on a many pixel MOS or CMOS readout array where the photodiode structure is chosen to include responses in the near infrared spectral ranges. A preferred embodiment incorporates a microcrystalline copper indium diselenide/cadmium sulfide photodiode structure on a CMOS readout array. An alternate preferred embodiment incorporates a microcrystalline silicon germanium photodiode structure on a CMOS readout array. Each of these embodiments provides night vision with image performance that greatly surpasses the GEN III night vision technology in terms of enhanced sensitivity, pixel size and pixel count.

Abstract: The present invention provides a MOS or CMOS based active sensor array for producing electronic images from charge producing light. Each pixel of the array includes a layered photodiode for converting the light into electrical charges and MOS and/or CMOS pixel circuits located under the layered photodiodes for collecting the charges. The present invention also provides additional MOS or CMOS circuits in and/or on the same crystalline substrate for processing the collected charges for the purposes of producing images. The layered photodiode of each pixel is fabricated as continuous layers of charge generating material on top of the MOS and/or CMOS pixel circuits so that extremely small pixels are possible with almost 100 percent packing factors. In preferred embodiments, pixel crosstalk is minimized by careful design of the bottom photodiode layer with the addition of carbon to the doped amorphous silicon N or P layer to increase the electrical resistivity.