Abstract: A pixel array substrate including a substrate and pixel units arranged in an array on the substrate is provided. Each pixel unit includes a TFT having a source, a gate, and a drain, a pixel electrode electrically connected to the drain, a common electrode, an insulation layer, and a test electrode. The pixel electrode is located between the common electrode and the substrate. The common electrode has slits that expose the pixel electrode. The insulation layer is located between the common electrode and the pixel electrode and has a contact hole exposing the pixel electrode. The test electrode and the common electrode belong to the same film layer, and the test electrode is separated from the common electrode. The contact hole is filled with the test electrode, and the test electrode is electrically connected to the drain. A display panel including the pixel array substrate is also provided.

Abstract: A display panel includes a plurality of rows of pixels, a gate driving circuit, and an inspection circuit. The gate driving circuit includes a plurality of gate driving units. The inspection circuit includes a plurality of transistors. Each transistor includes a first terminal, a control terminal, and a second terminal. The first terminal of the transistor is coupled to a contact pad. The control terminal of the transistor is coupled to the corresponding gate driving unit and a corresponding row of pixels. The second terminal of the transistor is coupled to the control terminal of the transistor.

Abstract: A display panel includes a plurality of rows of pixels, a gate driving circuit, and an inspection circuit. The gate driving circuit includes a plurality of gate driving units. The inspection circuit includes a plurality of transistors. Each transistor includes a first terminal, a control terminal, and a second terminal. The first terminal of the transistor is coupled to a contact pad. The control terminal of the transistor is coupled to the corresponding gate driving unit and a corresponding row of pixels. The second terminal of the transistor is coupled to the control terminal of the transistor.

Abstract: A pixel array substrate including a substrate and pixel units arranged in an array on the substrate is provided. Each pixel unit includes a TFT having a source, a gate, and a drain, a pixel electrode electrically connected to the drain, a common electrode, an insulation layer, and a test electrode. The pixel electrode is located between the common electrode and the substrate. The common electrode has slits that expose the pixel electrode. The insulation layer is located between the common electrode and the pixel electrode and has a contact hole exposing the pixel electrode. The test electrode and the common electrode belong to the same film layer, and the test electrode is separated from the common electrode. The contact hole is filled with the test electrode, and the test electrode is electrically connected to the drain. A display panel including the pixel array substrate is also provided.