Patents by Inventor Tzu-Chiang Yu

Tzu-Chiang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6043131
    Abstract: A method of forming a flower shaped capacitor for a DRAM over a bitline is disclosed. The method comprises the steps of: forming a first polysilicon layer over said bitline; forming a TEOS layer over said first polysilicon layer, patterning and etching an opening through said TEOS layer; depositing a second polysilicon layer; etching back said second polysilicon layer and the first polysilicon layer to form sidewall spacers in said opening; using the first polysilicon layer and sidewall spacers as a mask, etching through to said bitline and thereby removing said TEOS layer; depositing a third polysilicon layer; patterning and etching the third polysilicon layer to form a bottom storage node of the capacitor; and forming a dielectric layer and a top conductive layer over the bottom storage node.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: March 28, 2000
    Assignee: Worldwide Semiconductor Manufacturing Corporation
    Inventor: Tzu-Chiang Yu
  • Patent number: 5728622
    Abstract: A process for forming a narrow field oxide layer with a greater thickness. A silicon substrate is provided on which a layer of pad oxide and a layer of nitride are formed. Then, at least a wide area and a narrow area are defined on the silicon substrate through openings on the nitride layer. A thermal oxidation process is performed so as to grow a first oxide layer on the wide area and a second oxide layer on the narrow area. A polysilicon layer is then deposited over the entire surface. After that, chemical-mechanical polish (CMP) is applied so as to rub away part of the polysilicon layer that is lying above a plane coincident with the topmost surface of the nitride layer, thereby leaving a first polysilicon layer on the first oxide layer and a second polysilicon layer on the second oxide layer. A thermal oxidation process is performed so as to oxidize the first polysilicon layer and the second polysilicon layer, thereby increasing the thickness of the first oxide layer and the second oxide layer.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: March 17, 1998
    Assignee: Winbond Electronics Corporation
    Inventor: Tzu-Chiang Yu
  • Patent number: 5712183
    Abstract: A method of fabricating a via, that reduces contact resistance between two conductive layers. A conductive layer is formed at the periphery of a top surface of a gate. An insulating layer is formed over the gate, and is etched to form a via exposing the top surface of the gate and portions of the conductive layer. The top surface of the gate and the exposed conductive layer form a step profile, which provides extra contact area without increasing the lateral extent of the via.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: January 27, 1998
    Assignee: Winbond Electronics Corporation
    Inventor: Tzu-Chiang Yu
  • Patent number: D549136
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: August 21, 2007
    Inventor: Tzu-Chiang Yu
  • Patent number: D607479
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: January 5, 2010
    Assignee: DXG Technology Corp.
    Inventor: Tzu Chiang Yu
  • Patent number: D729656
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 19, 2015
    Assignee: DXG TECHNOLOGY CORP.
    Inventor: Tzu-Chiang Yu