Patents by Inventor Tzu-Chieh WEI

Tzu-Chieh WEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240038597
    Abstract: A method and a system for detecting a semiconductor device are provided. The method comprises obtaining an image of the semiconductor device, evaluating a feature of the image, detecting a defect of the semiconductor device based on the feature, extracting a defect information for the defect, calculating a defect die ratio (DDR) in response to the defect and analyzing a relation between the DDR and the defect information.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: FAN HU, WEN-CHUAN TAI, HSIANG-FU CHEN, I-CHIEH HUANG, TZU-CHIEH WEI, KANG-YI LIEN
  • Publication number: 20230308058
    Abstract: An amplifying circuit, comprising: a charging circuit, comprising a plurality of first transistors electrically coupled to a target device; and an output circuit, comprising a plurality of second transistors electrically coupled to the target device. After at least one of the first transistors turns on and the second transistors turn off such that the charging circuit charges the target device to a predetermined voltage, at least one of the first transistors and at least one of the second transistors simultaneously turn on for a predetermined time, and then at least one of the second transistors turns on but the first transistors turns off.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 28, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventor: Tzu-Chieh Wei
  • Publication number: 20230208363
    Abstract: Audio amplifier circuit includes a pulse width modulation circuit, an auxiliary loop circuit corresponding to a first variable resistance value and a first variable current value, and a main loop circuit corresponding to a second variable resistance value and a second variable current value. Main loop circuit is coupled between a second node, an output terminal, and a first node. Under a condition that auxiliary loop circuit and main loop circuit are turned on, second variable resistance value is decreased and second variable current value is increased after auxiliary loop circuit enters into a first control state, such that main loop circuit enters into a second control state. First variable resistance value is increased and first variable current value is decreased after main loop circuit enters into second control state, such that auxiliary loop circuit is out of first control state.
    Type: Application
    Filed: May 11, 2022
    Publication date: June 29, 2023
    Inventor: Tzu-Chieh WEI