Patents by Inventor Tzu Chun Lin
Tzu Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955441Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.Type: GrantFiled: March 28, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
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Publication number: 20240113112Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Patent number: 11949043Abstract: A micro light-emitting diode is provided. The micro light-emitting diode includes a first-type semiconductor layer having a first doping type; a light-emitting layer over the first-type semiconductor layer; a first-type electrode over the first-type semiconductor layer; a second-type semiconductor layer having a second doping type over the light-emitting layer, wherein the second doping type is different from the first doping type; a second-type electrode over the second-type semiconductor layer; and a barrier layer under the first-type semiconductor layer and away from the first-type electrode and the second-type electrode, wherein the barrier layer includes a doped region having the second doping type.Type: GrantFiled: October 29, 2020Date of Patent: April 2, 2024Assignee: PLAYNITRIDE DISPLAY CO., LTD.Inventors: Yen-Chun Tseng, Tzu-Yang Lin, Jyun-De Wu, Fei-Hong Chen, Yi-Chun Shih
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Publication number: 20240079451Abstract: A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and first and second dielectric walls. The substrate includes first and second fins. The first and second stacks of semiconductor nanosheets are disposed on the first and second fins respectively. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first and second strained layers are respectively disposed on the first and second fins and abutting the first and second stacks of semiconductor nanosheets. The first dielectric wall is disposed on the substrate and located between the first and second strained layers. The second dielectric wall is disposed on the first dielectric wall and located between the first and second strained layers. A top surface of the second dielectric wall is lower than top surfaces of the first and second strained layers.Type: ApplicationFiled: January 6, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ta-Chun Lin, Tzu-Hung Liu, Chun-Jun LIN, Chih-Hao Chang, Jhon Jhy Liaw
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Patent number: 11923413Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.Type: GrantFiled: February 7, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
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Publication number: 20240068119Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.Type: ApplicationFiled: March 2, 2023Publication date: February 29, 2024Applicant: Acer IncorporatedInventors: Tzu-Wei Lin, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
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Publication number: 20240047435Abstract: A luminous panel includes a circuit board, a plurality of connecting pads, a chip and two alignment structures. The connecting pads are located on the circuit board. The chip is located on the circuit board and at least partially covers the connecting pads. The two alignment structures are located on the circuit board. The two alignment structures and the connecting pads are at the same level. The two alignment structures are located at two diagonal corners of the chip. At least one part of the two alignment structures protrudes from the outline of the chip.Type: ApplicationFiled: December 27, 2022Publication date: February 8, 2024Inventors: Tzu-Chun LIN, Sheng-Yen CHENG, Jia-Hong WANG, Yueh-Hung CHUNG, Ya-Ling HSU, Chen-Hsien LIAO
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Patent number: 10173407Abstract: A device is for removing a first substrate from a second substrate or adhering the first substrate to the second substrate. The device includes a carrier, a flexible member and a supporting member. The carrier is for fixing the first substrate. The flexible member is for fixing the second substrate. The supporting member is connected to the carrier and the flexible member. The carrier and the flexible member are spaced a distance from each other. The carrier, the flexible member and the supporting member together define a first variable pressure chamber. The first variable pressure chamber has a first air hole.Type: GrantFiled: April 21, 2016Date of Patent: January 8, 2019Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chen-Chu Tsai, Cheng-Yi Wang, Shi-Chang Chen, Tzu-Chun Lin
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Publication number: 20170144422Abstract: A device is for removing a first substrate from a second substrate or adhering the first substrate to the second substrate. The device includes a carrier, a flexible member and a supporting member. The carrier is for fixing the first substrate. The flexible member is for fixing the second substrate. The supporting member is connected to the carrier and the flexible member. The carrier and the flexible member are spaced a distance from each other. The carrier, the flexible member and the supporting member together define a first variable pressure chamber. The first variable pressure chamber has a first air hole.Type: ApplicationFiled: April 21, 2016Publication date: May 25, 2017Inventors: Chen-Chu Tsai, Cheng-Yi Wang, Shi-Chang Chen, Tzu-Chun Lin
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Patent number: 9607809Abstract: A plasma reactor includes an enclosure having a top and a bottom and defining a processing chamber. Inlets are formed in the enclosure for injecting process gas into the chamber. An outlet is formed in the enclosure for withdrawing gas from the chamber. A platform is positioned to support a wafer in the chamber above the bottom. A plurality of coils is positioned above the top of the chamber. Each coil is coupled to a radio frequency generator.Type: GrantFiled: March 12, 2014Date of Patent: March 28, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Ching Lo, Po-Hsiung Leu, Tzu-Chun Lin, Ding-I Liu, Jen-Chi Chang, Ho-Ta Chuang
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Publication number: 20140273537Abstract: A plasma reactor includes an enclosure having a top and a bottom and defining a processing chamber. Inlets are formed in the enclosure for injecting process gas into the chamber. An outlet is formed in the enclosure for withdrawing gas from the chamber. A platform is positioned to support a wafer in the chamber above the bottom. A plurality of coils is positioned above the top of the chamber. Each coil is coupled to a radio frequency generator.Type: ApplicationFiled: March 12, 2014Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Ching LO, Po-Hsiung LEU, Tzu-Chun LIN, Ding-I LIU, Jen-Chi CHANG, Ho-Ta CHUANG
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Publication number: 20080259060Abstract: A video connection line to integrate digital and analog signals includes a first video connection port (may be one conforming to DVI-I specification) to transmit digital and analog signals that is divided to be coupled with a second video connection port (may be one conforming to DVI-D specification) to transmit digital video signals and a third video connection port (may be one conforming to VGA. D-SUB specifications) to transmit analog video signals. Thereby the DVI-I connection port supporting the digital and analog signals can be connected to a computer to output digital and analog signals at the same time to be used by the second and third connection ports, and displayed on different display devices.Type: ApplicationFiled: April 18, 2007Publication date: October 23, 2008Inventor: Tzu-Chun Lin
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Publication number: 20030008804Abstract: A graft copolymer of acrylic acid and maleic acid (or anhydride) grafted onto starch, a detergent builder composition containing the graft copolymer and a method of preparing the graft copolymer. These novel starch graft copolymers are highly water-soluble and biodegradable, have strong chelation ability to calcium ions and magnesium ions, and strong pH buffering ability. The composition has no phosphate and aluminosilicate. The composition has excellent anti-redeposition, building, anti-filming, dispersing, threshold crystal-inhibiting and enzyme performance-improving properties.Type: ApplicationFiled: May 13, 2002Publication date: January 9, 2003Inventors: Qiu Xu, Tzu Chun Lin, Fenbao Zhang, Kuan Hsiu Hwu