Patents by Inventor Tzu-chun Tseng
Tzu-chun Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145498Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.Type: ApplicationFiled: January 4, 2023Publication date: May 2, 2024Inventors: Hao-Lin Yang, Fu-Sheng Kuo, Ching-Chun Wang, Hsiao-Hui Tseng, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240134155Abstract: An imaging optical lens assembly includes four lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element and a fourth lens element. Each of the four lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. At least one of all lens surfaces of the four lens elements is aspheric and has at least one inflection point.Type: ApplicationFiled: October 9, 2023Publication date: April 25, 2024Applicant: LARGAN PRECISION CO., LTD.Inventors: Yu-Tai TSENG, Yu-Chun KE, Kuo-Jui WANG, Tzu-Chieh KUO
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Publication number: 20240128216Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.Type: ApplicationFiled: January 4, 2023Publication date: April 18, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Ching-Chun Wang, Hsiao-Hui Tseng, Chen-Jong Wang, Dun-Nian Yaung
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Patent number: 11949043Abstract: A micro light-emitting diode is provided. The micro light-emitting diode includes a first-type semiconductor layer having a first doping type; a light-emitting layer over the first-type semiconductor layer; a first-type electrode over the first-type semiconductor layer; a second-type semiconductor layer having a second doping type over the light-emitting layer, wherein the second doping type is different from the first doping type; a second-type electrode over the second-type semiconductor layer; and a barrier layer under the first-type semiconductor layer and away from the first-type electrode and the second-type electrode, wherein the barrier layer includes a doped region having the second doping type.Type: GrantFiled: October 29, 2020Date of Patent: April 2, 2024Assignee: PLAYNITRIDE DISPLAY CO., LTD.Inventors: Yen-Chun Tseng, Tzu-Yang Lin, Jyun-De Wu, Fei-Hong Chen, Yi-Chun Shih
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Patent number: 11935871Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.Type: GrantFiled: August 30, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
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Publication number: 20210246334Abstract: A polishing composition according to the present invention includes: silica; an anionic water-soluble polymer; at least one compound selected from the group consisting of a phosphonate group-containing compound, a phosphate group-containing compound, and an amino group-containing compound; and a dispersing medium.Type: ApplicationFiled: April 26, 2021Publication date: August 12, 2021Applicant: FUJIMI INCORPORATEDInventor: Tzu-Chun TSENG
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Patent number: 11015087Abstract: A polishing composition according to the present invention includes: silica; an anionic water-soluble polymer; at least one compound selected from the group consisting of a phosphonate group-containing compound, a phosphate group-containing compound, and an amino group-containing compound; and a dispersing medium.Type: GrantFiled: September 17, 2018Date of Patent: May 25, 2021Assignee: FUJIMI INCORPORATEDInventor: Tzu-Chun Tseng
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Publication number: 20210047541Abstract: Provided is a polishing composition that allows carbon-added silicon oxide (SiOC) to be polished at a higher polishing speed than the polishing speed of silicon nitride (i.e., the selection ratio of SiOC/silicon nitride is high). A polishing composition containing spinous silica particles and a dispersing medium, in which the pH is less than 5.Type: ApplicationFiled: March 13, 2019Publication date: February 18, 2021Applicant: FUJIMI INCORPORATEDInventor: Tzu-Chun TSENG
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Publication number: 20190092974Abstract: A polishing composition according to the present invention includes: silica; an anionic water-soluble polymer; at least one compound selected from the group consisting of a phosphonate group-containing compound, a phosphate group-containing compound, and an amino group-containing compound; and a dispersing medium.Type: ApplicationFiled: September 17, 2018Publication date: March 28, 2019Applicant: FUJIMI INCORPORATEDInventor: Tzu-Chun TSENG
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Patent number: 8906789Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.Type: GrantFiled: April 30, 2013Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun Hsiung Tsai, Yi-Fang Pai, Chien-Chang Su, Tzu-Chun Tseng, Meng-Yueh Liu
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Publication number: 20140264348Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.Type: ApplicationFiled: April 30, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.Inventors: Chun Hsiung Tsai, Yi-Fang Pai, Chien-Chang Su, Tzu-Chun Tseng, Meng-Yueh Liu
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Publication number: 20080067681Abstract: An interconnection structure is provided. The interconnection structure includes a substrate, a conductive barrier layer, a dielectric layer and a carbon nanotube. A conductive region is disposed in the substrate. The conductive barrier layer is disposed over the conductive region and the conductive barrier layer includes iron, cobalt or nickel. The dielectric layer is disposed on the substrate. The carbon nanotube is disposed in the dielectric layer to electrically connect with the conductive barrier layer.Type: ApplicationFiled: June 1, 2007Publication date: March 20, 2008Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Tzu-chun Tseng, Tri-Rung Yew, Chung-Min Tsai