Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

Abstract: The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a titanium layer, and a WNX layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.

Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

Abstract: A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.

Abstract: The present invention provides a method for manufacturing a stacked gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a metal layer, a barrier layer, and a tungsten layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.

Abstract: The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a titanium layer, and a WNX layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.

Abstract: A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.

Abstract: A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.

Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

Abstract: A manufacturing method for a shallow trench isolation region with high aspect ratio. The method comprises the steps of providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by high density plasma chemical vapor deposition (HDPCVD), removing the majority of the first insulation layer outside the trench by spray type etching, and forming a second insulation layer on the first insulation layer by low pressure CVD to fill the trench. According to the present invention, a void-free shallow trench isolation with high aspect ration can be achieved.

Abstract: A method of forming a high aspect ratio shallow trench isolation in a semiconductor substrate. The method includes the steps of forming a hard mask layer with a certain pattern on the semiconductor substrate, etching a portion of the semiconductor substrate not covered by the hard mask layer to form a high aspect ratio shallow trench in the semiconductor substrate; forming an oxide liner on the bottom and sidewall of the high aspect ratio shallow trench; performing a LPCVD to form a first oxide layer to fill the high aspect ratio shallow trench, a void being formed in the first oxide layer; etching a portion of the first oxide layer to a certain depth of the high aspect ratio shallow trench and to expose the void; and performing a HDPCVD to form a second oxide layer to fill the high aspect ratio shallow trench.

Abstract: A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench by spin-spraying to cover the oxide layer in the trench. An etchant is then sprayed over the surface of the semiconductor substrate to remove the uncovered oxide layer and expose the surface of the semiconductor substrate. The density of the etchant is less than that of the liquid etching shield. A second oxide layer is deposited in the trench to form isolation without voids or seams.

Abstract: A method for forming shallow trench isolation. A substrate is provided with a mask layer formed thereon. The mask layer is etched to expose a portion of the substrate, and the portion of the substrate is etched to form a trench. A liner layer is formed on the inside wall of the trench. A first dielectric layer and a sacrificial layer are sequentially deposited on the substrate such that the trench is substantially filled, wherein the first dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). Portions of the first dielectric layer and the sacrificial layer are removed from the trench. A second dielectric layer is deposited on the substrate such that the trench is substantially filled, wherein the second dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). A portion of the second dielectric layer is removed from the trench.

Abstract: A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.

Abstract: A method for forming shallow trench isolation. A substrate is provided with a mask layer formed thereon. The mask layer is etched to expose a portion of the substrate, and the portion of the substrate is etched to form a trench. A liner layer is formed on the inside wall of the trench. A first dielectric layer and a sacrificial layer are sequentially deposited on the substrate such that the trench is substantially filled, wherein the first dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). Portions of the first dielectric layer and the sacrificial layer are removed from the trench. A second dielectric layer is deposited on the substrate such that the trench is substantially filled, wherein the second dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). A portion of the second dielectric layer is removed from the trench.

Abstract: A manufacturing method for a shallow trench isolation region with high aspect ratio. The method comprises the steps of providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by high density plasma chemical vapor deposition (HDPCVD), removing the majority of the first insulation layer outside the trench by spray type etching, and forming a second insulation layer on the first insulation layer by low pressure CVD to fill the trench. According to the present invention, a void-free shallow trench isolation with high aspect ration can be achieved.

Abstract: A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench by spin-spraying to cover the oxide layer in the trench. An etchant is then sprayed over the surface of the semiconductor substrate to remove the uncovered oxide layer and expose the surface of the semiconductor substrate. The density of the etchant is less than that of the liquid etching shield. A second oxide layer is deposited in the trench to form isolation without voids or seams.

Abstract: A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.

Abstract: A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.