Abstract: Embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (EPI), transistors, and silicon substrate. The isolation structures are arranged in a pattern with a long isolation structure adjacent a short isolation structure. The isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.

Abstract: A method includes forming a plurality of semiconductor regions, forming a plurality of gate stacks, wherein the plurality of gate stacks are on first portions of the plurality of semiconductor regions, and etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks. The plurality of openings include a first opening in a first gate stack, and a second opening in a second gate stack. The first opening and the second opening are immediately neighboring each other and have an overlap with an overlap distance equal to or greater than a pitch of the plurality of semiconductor regions. The plurality of semiconductor regions are etched to extend the plurality of openings downwardly to be between dielectric isolation regions, followed by filling the plurality of openings to form fin isolation regions. The gate isolations are spaced part from the fin isolation regions.

Abstract: A structure includes a plurality of semiconductor regions, a first gate stack and a second gate stack immediately neighboring each other, a first fin isolation region in the first gate stack, and a second fin isolation region in the second gate stack. The first fin isolation region and the second fin isolation region have a sideway overlap having an overlap distance being equal to or greater than a pitch of the plurality of semiconductor regions. The overlap distance is measured in a direction parallel to lengthwise directions of the first gate stack and the second gate stack. A plurality of source/drain regions are on opposing sides of the first gate stack and the second gate stack to form a plurality of transistors.

Abstract: Methods for isolating two adjacent transistors are disclosed. A substrate has a first semiconducting fin on a first region and a second semiconducting fin on a second region, and the first semiconducting fin and the second semiconducting fin contact each other at a jog region. A dummy gate within or adjacent the jog region is removed to expose a portion of the first semiconducting fin and form an isolation volume. Etching is performed to remove the exposed portion of the first semiconducting fin and create a trench in the substrate. The trench and the isolation volume are filled with at least one dielectric material to form an electrically isolating structure between the first region and the second region. Additional dummy gates in each region can be removed and replaced with an electrically conductive material to form two adjacent transistors electrically isolated from each other.

Abstract: Embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (EPI), transistors, and silicon substrate. The isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.

Abstract: The present disclosure describes a semiconductor device having a dielectric fin structure. The semiconductor device includes a channel structure on a substrate and a dielectric fin structure on the substrate and adjacent to the channel structure. The channel structure extends along a first direction. The dielectric fin structure includes a stiff dielectric material and extends along a second direction parallel to the first direction. The semiconductor device further includes an isolation structure extending through the channel structure. The isolation structure is in contact with the dielectric fin structure.

Abstract: Continuous polysilicon on oxide diffusion edge (CPODE) processes are described herein in which one or more semiconductor device parameters are tuned to reduce the likelihood of etching of source/drain regions on opposing sides of CPODE structures formed in a semiconductor device, to reduce the likelihood of depth loading in the semiconductor device, and/or to reduce the likelihood of gate deformation in the semiconductor device, among other examples. Thus, the CPODE processes described herein may reduce the likelihood of epitaxial damage to the source/drain regions, may reduce current leakage between the source/drain regions, and/or may reduce the likelihood of threshold voltage shifting for transistors of the semiconductor device. The reduced likelihood of threshold voltage shifting may provide more uniform and/or faster switching speeds for the transistors, more uniform and/or lower power consumption for the transistors, and/or increased device performance for the transistors, among other examples.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a substrate, a source/drain feature disposed over the substrate, a gate spacer disposed over the source/drain feature, and a first isolation trench structure disposed over the substrate. The first isolation trench includes an upper portion adjacent to the gate spacer, a middle portion disposed below the upper portion and adjacent to a first side of the source/drain feature, and a lower portion disposed below the middle portion and extending into the substrate, wherein the lower portion has a bowing profile extending outwardly from one side of the first isolation trench structure.

Abstract: A continuous metal on diffusion edge (CMODE) may be used to form a CMODE structure in a semiconductor device after a replacement gate process that is performed to replace the polysilicon dummy gate structures of the semiconductor device with metal gate structures. The CMODE process described herein includes removing a portion of a metal gate structure (as opposed to removing a portion of a polysilicon dummy gate structure) to enable formation of the CMODE structure in a recess left behind by removal of the portion of the metal gate structure.

Abstract: Methods for fabricating semiconductor devices are provided. An exemplary method includes forming fins in a dense region and in an isolated region of a semiconductor substrate; performing a plasma dry etch process to remove a portion of at least one selected fin to form a first trench in the dense region and to remove a portion of at least one selected fin in the isolated region to form a second trench in the isolated region, wherein the plasma dry etch process includes: performing a passivation-oriented process and an etchant-oriented process; and controlling the passivation-oriented process and the etchant-oriented process to form the first trench with a desired first critical dimension and first depth and to form the second trench with a desired second critical dimension and second depth.

Abstract: Provided are semiconductor devices and methods for fabricating such devices. An exemplary method includes forming a fin structure over a semiconductor material; forming a sacrificial layer over the semiconductor material; removing a portion of the fin structure and an overlying portion of the sacrificial layer located over the portion of the fin structure to form a trench; forming an insulation structure in the trench, wherein an adjacent portion of the sacrificial layer is adjacent an end wall of the insulation structure; removing the adjacent portion to form a cavity partially defined by the end wall; lining the cavity with a liner, wherein an end portion of the liner is located on the end wall of the insulation structure; filling the cavity with a fill material; removing the end portion of the liner to form an opening; and forming an end isolation structure in the opening.

Abstract: Semiconductor devices and methods of fabrication are provided. A method includes providing a semiconductor structure with a first sidewall distanced from a second sidewall, fins located between the first sidewall and the second sidewall, and isolation regions located between the first sidewall and the second sidewall, wherein adjacent fins are separated by a respective isolation region. The method further includes performing a plasma etching process to etch the fins and the isolation regions, wherein the plasma etching process chemically etches the fins, wherein the plasma etching process physically etches the isolation regions to recesses defining a crown-shaped depth profile.

Abstract: Devices with metal structures formed with seams and methods of fabrication are provided. An exemplary method includes forming a metal plug having a top surface formed with a seam; depositing a film over the top surface of the metal plug and at least partially filling the seam; and etching the film from over the metal plug, wherein the film remains in the seam.

Abstract: Provided are semiconductor devices with isolation structures and methods for fabricating such devices. An exemplary method includes forming an isolation layer over a semiconductor material; forming source/drain regions over the isolation layer; removing a selected gate structure, wherein removing the selected gate structure forms a trench in the semiconductor material; and forming an isolation structure in the trench.

Abstract: A semiconductor structure may be provided by: forming semiconductor fins over a semiconductor substrate; forming a gate dielectric layer and gate electrodes; forming a silicon layer over the gate electrodes; forming a dielectric mask layer including openings over the silicon layer; etching portions of the silicon layer that underlie the openings by performing a first anisotropic etch process; etching portions of the gate electrodes that underlie the openings by performing a second anisotropic etch process; and removing portions of the semiconductor fins and portions of the semiconductor substrate that underlie the openings by performing a third anisotropic etch process. At least one anisotropic etch step within the third anisotropic etch process comprises at least one low pressure etch step that is performed at a total pressure in a range from 5 mTorr to 50 mTorr.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a first fin and around first channel regions that are disposed over the first fin; forming an interlayer dielectric (ILD) layer over the first fin around the dummy gate structure; replacing the dummy gate structure with a gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the first fin, where the first and second dielectric plugs cut the gate structure into a plurality of segments separated from each other; removing a segment of the gate structure interposed between the first dielectric plug and the second dielectric plugs to expose the first channel regions; removing the exposed first channel regions, where after removing the exposed first channel regions, a recess is formed in the ILD layer; and filling the recess with a dielectric material.

Abstract: A method includes forming a gate stack on a semiconductor region, wherein the semiconductor region is over a bulk semiconductor substrate. The gate stack is etched to form a first trench, wherein a plurality of protruding semiconductor fins are revealed to the first trench. The plurality of protruding semiconductor fins are etched to form a plurality of second trenches extending into the bulk semiconductor substrate. The plurality of second trenches are underlying and joined to the first trench. The plurality of second trenches include a first outmost trench having a first depth, a second outmost trench, and an inner trench between the first outmost trench and the second outmost trench. The inner trench has a second depth equal to or smaller than the first depth. A fin isolation region is formed to fill the first trench and the plurality of second trenches.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured layers on first and second fin bases, forming cladding layers on sidewalls of the first and second nanostructured layers, forming a polysilicon structure on the first and second nanostructured layers, removing a portion of the polysilicon structure to form a first opening on the second nanostructured layers, removing a portion of the second nanostructured layers through the first opening to form a second opening on the second fin base, removing a portion of the second fin base through the second opening to form a third opening on the substrate, removing a portion of the substrate through the third opening to form a fourth opening in the substrate, and depositing an insulation material to fill the first, second, third, and fourth openings.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed. The fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure.

Abstract: Methods for forming a CPODE structure with reduced leakage current are disclosed herein. The CPODE structure is formed by etching away a pair of fins and forming a pair of trenches in the substrate where the pair of fins was originally located. A leakage path may be present in the area between the pair of fins. The etching is performed by cycling continuously plasma etch until the trenches are formed. The plasma etch removes any byproducts that may be formed during the fin etch which could reduce or stop the etching of the fins, the area between the pair of fins, and the substrate.