Abstract: A method of controlling a feedback control system of a semiconductor process chemical fluid in a storage tank includes performing a fluid quality measurement of fluid by a spectrum analyzer positioned adjacent to a dispensing port of the storage tank, and determining whether a variation in fluid quality measurement of the fluid is within an acceptable range. The method further includes in response to a variation in fluid quality measurement that is not within the acceptable range of variation in fluid quality measurement, automatically adjusting a configurable parameter of the semiconductor process chemical fluid in the storage tank to set the variation in fluid quality measurement of the fluid within the acceptable range.

Abstract: A dispensing system includes a dispense material supply that contains a dispense material and a dispensing pump connected downstream from the dispense material supply. The dispensing pump includes a body made of a first electrically conductive material, one or more first electrical contacts that are disposed on the body of the dispensing pump, and one or more first connection wires that are coupled between each one of the one or more first electrical contacts and ground. The dispensing system also includes a dispensing nozzle connected downstream from the dispensing pump and includes a tube made of a second electrically conductive material, one or more second electrical contacts that are disposed on an outer surface of the tube, and one or more second connection wires that are coupled between each one of the one or more second electrical contacts and the ground.

Abstract: Some embodiments relate to an IC device, including a first chip comprising a plurality of pixel blocks respectively including one of a first plurality of conductive pads, the plurality of pixel blocks arranged in rows extending in a first direction and columns extending in a second direction perpendicular to the first direction; a second chip bonded to the first chip at a bonding interface, where the second chip comprises a second plurality of conductive pad recessed and contacting the first plurality of conductive pads along the bonding interface; and a first corrugated shield line having outermost edges set-back along the second direction from outermost edges of a first row of the plurality of pixel blocks, the first corrugated shield line being arranged within a first dielectric layer and laterally separating neighboring ones of the first plurality of conductive pads within the first row of the plurality of pixel blocks.

Abstract: A semiconductor light-emitting device including a light-emitting diode chip and an electrode disposed thereon is provided. The electrode at least includes a plated silver alloy (Ag1-xYx) layer, wherein the Y of the Ag1-xYx layer includes metals forming a complete solid solution with Ag at arbitrary weight percentage, and the X of the Ag1-xYx layer is in a range from about 0.02 to 0.15. The fabricating method thereof is also provided.

Abstract: A semiconductor light-emitting device including a light-emitting diode chip and an electrode disposed thereon is provided. The electrode at least includes a plated silver alloy (Ag1-xYx) layer, wherein the Y of the Ag1-xYx layer includes metals forming a complete solid solution with Ag at arbitrary weight percentage, and the X of the Ag1-xYx layer is in a range from about 0.02 to 0.15. The fabricating method thereof is also provided.

Abstract: A solder ball includes a silver ball structure and a shell structure. The shell structure wraps a surface of the silver ball structure, and a material of the shell structure at least includes tin. When the solder ball is bonded to other devices, the ball height of the solder ball remains constant to avoid collapse.

Abstract: A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au0.35Sn0.15 to about Au0.75Sn0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.

Abstract: A chip package structure including a chip, a circuit layer, a passive element material and a substrate is provided. The circuit layer is disposed on a surface of the chip, wherein the circuit layer includes a plurality of bumps and a plurality of passive element electrodes. The bumps and the passive element electrodes have the same material, and the passive element electrodes are electrically connected with part of the bumps. The passive element material is disposed between the passive element electrodes, so that the passive element electrodes and the passive element material form a passive element located on the surface of the chip. The chip is disposed on the substrate and faces the substrate by the surface, so that the chip and the passive element are electrically connected to the substrate through the bumps. A method of manufacturing the chip package structure aforementioned is also provided.

Abstract: A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn. alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling, with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au0.35Sn0.15 to about Au0.75Sn0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by reflow operation or a thermal press operation.

Abstract: A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au0.85Sn0.15 to about Au0.75Sn0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.

Abstract: A network device includes a first transceiver unit, a second transceiver unit and a control unit. The first transceiver unit is utilized for processing a data corresponding to a first physical (PHY) layer via a first interface. The second transceiver unit is utilized for processing a data corresponding to a second PHY layer via a second interface. The control unit is utilized for processing a data corresponding to a media access control (MAC) layer, wherein the control unit connects with at least one of the first transceiver unit and the second transceiver unit with reference to a connection scheme.

Abstract: A transceiver includes a transceiver and a clock generation unit. The clock generation unit includes a clock generator, a multiplexer, and a frequency difference detector. The transceiver exchanges data with a link partner according to a first clock generated by a phase-locked loop. The clock generator is used for generating and outputting a second clock. The multiplexer is used for receiving a calibration clock or a receiver clock of the link partner, and outputting the calibration clock or the receiver clock of the link partner. The frequency difference detector is used for generating a difference signal according to a difference between the calibration clock and the second clock, or a difference between the receiver clock of the link partner and the second clock. The clock generator adjusts the shift of the second clock according to the difference signal. The phase-locked loop generates the first clock according to the second clock.

Abstract: A communication apparatus is disclosed including: an analog-front-end circuit for receiving and processing an analog input signal; an analog-to-digital converter (ADC) coupled with the analog-front-end circuit for converting processed signal from the analog-front-end circuit into a digital input signal; and a control unit coupled with the ADC for adjusting at least one resistance and/or at least one capacitance in an analog echo cancellation circuit according to the digital input signal before the analog-front-end circuit receives a training sequence that is the first training sequence transmitted from a second communication apparatus after the second communication apparatus begins communicating with the communication apparatus.

Abstract: A data transmitting and receiving device and method are used for saving powers and maintaining the connection quality, stability and continuous link. The method includes the step of gradually adjusting the de-emphasis of the signal transmitted from the data transmitting and receiving device according to the setting value thereof. The method also includes the steps of transmitting training sequence signal with an amplitude and the default de-emphasis by the data transmitting and receiving device to the remote device, receiving the training sequence signal from the remote device, thereby the channel attenuation is estimated using the method, and a better de-emphasis is set up. Then, the data transmitting and receiving device gradually increases the amplitude of the training sequence signal and re-transmits it until the remote device receives the training sequence signal transmitted therefrom.

Abstract: A transceiver includes a transceiver and a clock generation unit. The clock generation unit includes a clock generator, a multiplexer, and a frequency difference detector. The transceiver exchanges data with a link partner according to a first clock generated by a phase-locked loop. The clock generator is used for generating and outputting a second clock. The multiplexer is used for receiving a calibration clock or a receiver clock of the link partner, and outputting the calibration clock or the receiver clock of the link partner. The frequency difference detector is used for generating a difference signal according to a difference between the calibration clock and the second clock, or a difference between the receiver clock of the link partner and the second clock. The clock generator adjusts the shift of the second clock according to the difference signal. The phase-locked loop generates the first clock according to the second clock.

Abstract: The disclosure provides an electronic device and a network access module. The electronic device comprises: a multimedia processing module and a network access module. The multi-media processing module comprises a first network control circuit, and the network access module comprises: a second network control circuit, a third network control circuit, at least a fourth network control circuit, a network transmission unit, and a multiplexer. The multiplexer is utilized for selecting at least a multimedia connecting port from a plurality of multimedia connecting ports to connect to the at least a fourth network control circuit, so as to make at least a multimedia device connected to the at least a multimedia connecting port to connect to an external network and access the external network via the at least a fourth network control circuit, the network transmission unit, the third network control circuit, and the network connecting port.

Abstract: A communication signal receiver includes an adder, a slicer, and an infinite impulse response (IIR) filter. The adder performs an addition on a first signal and a filtered signal to generate an output signal. The slicer performs a hard decision on the output signal to generate a detecting result. The IIR filter is coupled to the slicer and the adder for processing the output signal to generate the filtered signal. The communication signal receiver further includes a decoder. The decoder receives and decodes the output signal to generate a decoded output signal, wherein the decoder is a Viterbi decoder.

Abstract: A method for a mobile station to provide to a base station feedback of channel state information (CSI) regarding a plurality of communication channels between the mobile station and the base station. The method includes: estimating the CSI by calculating a plurality of channel responses each for one of the communication channels; compressing the estimated CSI; and sending the compressed CSI as the feedback to the base station.

Abstract: A communication apparatus is disclosed including: an analog-front-end circuit for receiving and processing an analog input signal; an analog-to-digital converter (ADC) coupled with the analog-front-end circuit for converting processed signal from the analog-front-end circuit into a digital input signal; and a control unit coupled with the ADC for adjusting at least one resistance and/or at least one capacitance in an analog echo cancellation circuit according to the digital input signal before the analog-front-end circuit receives a training sequence that is the first training sequence transmitted from a second communication apparatus after the second communication apparatus begins communicating with the communication apparatus.

Abstract: A network device includes a first transceiver unit, a second transceiver unit and a control unit. The first transceiver unit is utilized for processing a data corresponding to a first physical (PHY) layer via a first interface. The second transceiver unit is utilized for processing a data corresponding to a second PHY layer via a second interface. The control unit is utilized for processing a data corresponding to a media access control (MAC) layer, wherein the control unit connects with at least one of the first transceiver unit and the second transceiver unit with reference to a connection scheme.