Patents by Inventor Tzu-Hsiang HUNG
Tzu-Hsiang HUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20200185597Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.Type: ApplicationFiled: December 11, 2018Publication date: June 11, 2020Inventors: Kun-Ju Li, Hsin-Jung Liu, I-Ming Tseng, Chau-Chung Hou, Yu-Lung Shih, Fu-Chun Hsiao, Hui-Lin Wang, Tzu-Hsiang Hung, Chih-Yueh Li, Ang Chan, Jing-Yin Jhang
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Publication number: 20170217015Abstract: An industrial robot includes an actuator and a driver. The actuator serves to provide power inside so as to create a predetermined motional form. The driver serves to drive an internal power source of the actuator to output power. The driver is adjacently and fixedly connected with one end of the actuator. A power unit is disposed in the actuator for generating power. The power unit has an output shaft. The actuator has a transmission unit for transmitting the power to make an operation unit move in the predetermined motional form. The transmission unit has a transmission shaft. The output shaft and the transmission shaft are coaxially and integrally formed.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventors: Jhong - Siang LIOU, Chien-Nien TSAI, Li-Wei ZHENG, Yu-Hsiang LIN, Tzu-Hsiang Hung
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Publication number: 20160351674Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface. A semiconductor structure formed by said semiconductor process is also provided.Type: ApplicationFiled: August 9, 2016Publication date: December 1, 2016Inventors: Kun-Ju Li, Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Chih-Hsun Lin, Tzu-Hsiang Hung, Wu-Sian Sie, I-Lun Hung, Wen-Chin Lin, Chun-Tsen Lu
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Publication number: 20160268125Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.Type: ApplicationFiled: March 13, 2015Publication date: September 15, 2016Inventors: Kun-Ju Li, Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Chih-Hsun Lin, Tzu-Hsiang Hung, Wu-Sian Sie, I-Lun Hung, Wen-Chin Lin, Chun-Tsen Lu
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Patent number: 9443726Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.Type: GrantFiled: March 13, 2015Date of Patent: September 13, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Chih-Hsun Lin, Tzu-Hsiang Hung, Wu-Sian Sie, I-Lun Hung, Wen-Chin Lin, Chun-Tsen Lu
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Patent number: 9404816Abstract: A multifunctional load test device includes a drive, a motor to be tested, a load motor and an inverter. The drive is electrically connected to civil power. The motor to be tested is electrically connected to the drive and powered by the drive and controllably drivable by the drive. The load motor is drivable by the motor to be tested to produce counter electromotive force. The inverter is electrically connected to the load motor to rectify the counter electromotive force into power identical to civil power.Type: GrantFiled: June 6, 2015Date of Patent: August 2, 2016Assignee: HIWIN MIKROSYSTEM CORP.Inventors: Chi-Yuan Cheng, Wei-Cheng Wang, Tzu-Hsiang Hung
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Patent number: 9293394Abstract: An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.Type: GrantFiled: April 23, 2014Date of Patent: March 22, 2016Assignee: XINTEC INC.Inventors: Bai-Yao Lou, Tsang-Yu Liu, Chia-Sheng Lin, Tzu-Hsiang Hung
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Patent number: 8878367Abstract: A substrate structure with through vias is provided. The substrate structure with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the semiconductor substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.Type: GrantFiled: November 23, 2011Date of Patent: November 4, 2014Assignee: Xintec Inc.Inventors: Chia-Sheng Lin, Chien-Hui Chen, Bing-Siang Chen, Tzu-Hsiang Hung
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Publication number: 20140231966Abstract: An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.Type: ApplicationFiled: April 23, 2014Publication date: August 21, 2014Applicant: XINTEC INC.Inventors: Bai-Yao LOU, Tsang-Yu LIU, Chia-Sheng LIN, Tzu-Hsiang HUNG
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Patent number: 8786093Abstract: An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate.Type: GrantFiled: January 26, 2012Date of Patent: July 22, 2014Inventors: Chia-Sheng Lin, Tzu-Hsiang Hung
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Patent number: 8779452Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.Type: GrantFiled: September 1, 2011Date of Patent: July 15, 2014Inventors: Tzu-Hsiang Hung, Hsin-Chih Chiu, Chuan-Jin Shiu, Chia-Sheng Lin, Yen-Shih Ho, Yu-Min Liang
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Publication number: 20140154830Abstract: A method for forming an image sensor chip package includes: providing a substrate having predetermined scribe lines defined thereon, wherein the predetermined scribe lines define device regions and each of the device regions has at least a device formed therein; disposing a support substrate on a first surface of the substrate; forming at least a spacer layer between the support substrate and the substrate, wherein the spacer layer covers the predetermined scribe lines; forming a package layer on a second surface of the substrate; forming conducting structures on the second surface of the substrate, wherein the conducting structures are electrically connected to the corresponding device in corresponding one of the device regions, respectively; and dicing along the predetermined scribe lines such that the support substrate is removed from the substrate and the substrate is separated into a plurality of individual image sensor chip packages.Type: ApplicationFiled: February 5, 2014Publication date: June 5, 2014Applicant: XINTEC INC.Inventors: Yu-Lung HUANG, Tzu-Hsiang HUNG, Yen-Shih HO
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Patent number: 8742564Abstract: An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.Type: GrantFiled: January 13, 2012Date of Patent: June 3, 2014Inventors: Bai-Yao Lou, Tsang-Yu Liu, Chia-Sheng Lin, Tzu-Hsiang Hung
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Patent number: 8692358Abstract: A method for forming an image sensor chip package includes: providing a substrate having predetermined scribe lines defined thereon, wherein the predetermined scribe lines define device regions and each of the device regions has at least a device formed therein; disposing a support substrate on a first surface of the substrate; forming at least a spacer layer between the support substrate and the substrate, wherein the spacer layer covers the predetermined scribe lines; forming a package layer on a second surface of the substrate; forming conducting structures on the second surface of the substrate, wherein the conducting structures are electrically connected to the corresponding device in corresponding one of the device regions, respectively; and dicing along the predetermined scribe lines such that the support substrate is removed from the substrate and the substrate is separated into a plurality of individual image sensor chip packages.Type: GrantFiled: August 25, 2011Date of Patent: April 8, 2014Inventors: Yu-Lung Huang, Tzu-Hsiang Hung, Yen-Shih Ho
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Publication number: 20120193786Abstract: An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate.Type: ApplicationFiled: January 26, 2012Publication date: August 2, 2012Inventors: Chia-Sheng LIN, Tzu-Hsiang HUNG
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Publication number: 20120181672Abstract: An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.Type: ApplicationFiled: January 13, 2012Publication date: July 19, 2012Inventors: Bai-Yao LOU, Tsang-Yu LIU, Chia-Sheng LIN, Tzu-Hsiang HUNG
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Publication number: 20120133049Abstract: A method of fabricating a semiconductor device, a process of fabricating a through substrate via and a substrate with through vias are provided. The substrate with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.Type: ApplicationFiled: November 23, 2011Publication date: May 31, 2012Inventors: Chia-Sheng Lin, Chien-Hui Chen, Bing-Siang Chen, Tzu-Hsiang Hung
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Patent number: D784430Type: GrantFiled: December 15, 2015Date of Patent: April 18, 2017Assignee: HIWIN MIKROSYSTEM CORP.Inventors: Jhong-Siang Liou, Chien-Nien Tsai, Li-Wei Zheng, Yu-Hsiang Lin, Tzu-Hsiang Hung
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Patent number: D784431Type: GrantFiled: December 16, 2015Date of Patent: April 18, 2017Assignee: HIWIN MIKROSYSTEM CORP.Inventors: Jhong-Siang Liou, Chien-Nien Tsai, Li-Wei Zheng, Yu-Hsiang Lin, Tzu-Hsiang Hung