Patents by Inventor Tzu-Hsien Yang

Tzu-Hsien Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240371434
    Abstract: A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsien Yang, Chia-En Huang, Yih Wang, Jonathan Tsung-Yung Chang
  • Publication number: 20240363594
    Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsien Yang, Hiroki Noguchi, Mahmut Sinangil, Yih Wang
  • Publication number: 20240339467
    Abstract: Some embodiments relate to an IC device, including a first chip comprising a plurality of pixel blocks respectively including one of a first plurality of conductive pads, the plurality of pixel blocks arranged in rows extending in a first direction and columns extending in a second direction perpendicular to the first direction; a second chip bonded to the first chip at a bonding interface, where the second chip comprises a second plurality of conductive pad recessed and contacting the first plurality of conductive pads along the bonding interface; and a first corrugated shield line having outermost edges set-back along the second direction from outermost edges of a first row of the plurality of pixel blocks, the first corrugated shield line being arranged within a first dielectric layer and laterally separating neighboring ones of the first plurality of conductive pads within the first row of the plurality of pixel blocks.
    Type: Application
    Filed: April 7, 2023
    Publication date: October 10, 2024
    Inventors: Chi-Hsien Chung, Tzu-Jui Wang, Chia-Chi Hsiao, Kuan-Chieh Huang, Wei-Cheng Hsu, Hao-Lin Yang, Yi-Han Liao, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20240332420
    Abstract: A method includes forming a gate stack for a short-channel device and a longer-channel device; forming a first metal cap layer over the gate stacks for the short-channel device and the longer-channel device, wherein the first metal cap layer of the longer-channel device has a metal-cap recess; forming a first dielectric cap layer in the metal-cap recess; selectively removing in parallel, a portion of the gate stacks and first metal cap layer for the short-channel device and the longer-channel device; forming a first channel recess between spacers in the short-channel device and a second channel recess between a spacer and the first dielectric cap layer in the longer-channel device by the selectively removing; wherein each of the first channel recess and the second channel recess has a width dimension and a difference between the width dimensions of the first channel recess and second channel recess is less than 3 nm.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh CHAO, Ryan Chia-Jen CHEN, Yih-Ann LIN, Yu-Hsien LIN, Li-Wei YIN, Tzu-Wen PAN, Jih-Sheng YANG
  • Publication number: 20240321739
    Abstract: Provided are structures and methods for forming structures with surfaces having a W-shaped profile. An exemplary method includes differentially etching a gate material to a recessed surface including a first and second horn and a valley located therebetween including first and second sections and a middle section therebetween; depositing an etch-retarding layer over the recessed surface including first and second edge regions and a central region therebetween, wherein the first edge region is located over the first horn and the first section, the second edge region is located over the second horn and the second section, the central region is located over the middle region, and the central region is thicker than the first edge region and the second edge region; and performing an etch process to recess the horns to establish the gate material with a W-shaped profile.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jih-Sheng Yang, Li-Wei Yin, Yu-Hsien Lin, Tzu-Wen Pan, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Patent number: 12087354
    Abstract: A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsien Yang, Chia-En Huang, Yih Wang, Jonathan Tsung-Yung Chang
  • Patent number: 12068284
    Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hsien Yang, Hiroki Noguchi, Mahmut Sinangil, Yih Wang
  • Publication number: 20240243105
    Abstract: A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).
    Type: Application
    Filed: March 28, 2024
    Publication date: July 18, 2024
    Inventors: Tzu-Hsien Yang, Hiroki Noguchi, Hidehiro Fujiwara, Yih Wang
  • Patent number: 11978723
    Abstract: A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hsien Yang, Hiroki Noguchi, Hidehiro Fujiwara, Yih Wang
  • Publication number: 20240147711
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
  • Patent number: 11955960
    Abstract: The invention uses the control circuit formed on the silicon wafer to detect the leakage current of transistor formed on the depletion mode GaN wafer and then adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current. Essentially, the gate voltage is reduced or viewed as made more negative when the detected leakage current is larger a specific value. Thus, the gate voltage can be gradually adjusted to approach a specific threshold voltage that right block the leakage current. In other words, by making the gate voltage more negative when non-zero leakage current is detected and even by making the gate voltage more positive when zero leakage current is detected, the depletion mode GaN transistor can be adjusted to have an acceptable or even zero leakage current, a high reaction rate and an optimized efficiency.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: April 9, 2024
    Assignee: CHIP-GAN POWER SEMICONDUCTOR CORPORATION
    Inventors: Ke-Horng Chen, Tzu-Hsien Yang, Yong-Hwa Wen, Kuo-Lin Cheng
  • Publication number: 20240072790
    Abstract: The invention uses the control circuit formed on the silicon wafer to detect the leakage current of transistor formed on the depletion mode GaN wafer and then adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current. Essentially, the gate voltage is reduced or viewed as made more negative when the detected leakage current is larger a specific value. Thus, the gate voltage can be gradually adjusted to approach a specific threshold voltage that right block the leakage current. In other words, by making the gate voltage more negative when non-zero leakage current is detected and even by making the gate voltage more positive when zero leakage current is detected, the depletion mode GaN transistor can be adjusted to have an acceptable or even zero leakage current, a high reaction rate and an optimized efficiency.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: KE-HORNG CHEN, TZU-HSIEN YANG, YONG-HWA WEN, KUO-LIN CHENG
  • Patent number: 11903188
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Perng-Fei Yuh, Yih Wang, Meng-Sheng Chang, Jui-Che Tsai, Ku-Feng Lin, Yu-Wei Lin, Keh-Jeng Chang, Chansyun David Yang, Shao-Ting Wu, Shao-Yu Chou, Philex Ming-Yan Fan, Yoshitaka Yamauchi, Tzu-Hsien Yang
  • Publication number: 20230262969
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
  • Publication number: 20230134975
    Abstract: A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.
    Type: Application
    Filed: March 2, 2022
    Publication date: May 4, 2023
    Inventors: Tzu-Hsien Yang, Chia-En Huang, Yih Wang, Jonathan Tsung-Yung Chang
  • Publication number: 20230021750
    Abstract: A radio frequency rectifier circuit including a rectifier circuit and a controller circuit is provided. The rectifier circuit receives a radio frequency signal and converts the radio frequency signal into a direct-current voltage serving as an output voltage. The rectifier circuit includes multiple power stages and multiple switch circuits. Each of the switch circuits is coupled between two of the power stages. The controller circuit is coupled to the rectifier circuit. The controller circuit outputs a control signal to control a conduction number of the switch circuits according to a value of the output voltage.
    Type: Application
    Filed: May 20, 2022
    Publication date: January 26, 2023
    Applicant: E Ink Holdings Inc.
    Inventors: Zi-Yu Zeng, Tzu-Hsien Yang, Chong-Sin Huang, Zheng-Lun Huang, Ke-Horng Chen, Pin-Cheng Chiu, Chuen-Jen Liu, Chi-Mao Hung
  • Patent number: 11526328
    Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: December 13, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hung-Sheng Chang, Han-Wen Hu, Hsiang-Pang Li, Tzu-Hsien Yang, I-Ching Tseng, Hsiang-Yun Cheng, Chia-Lin Yang
  • Publication number: 20220328455
    Abstract: A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).
    Type: Application
    Filed: November 30, 2021
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsien Yang, Hiroki Noguchi, Hidehiro Fujiwara, Yih Wang
  • Publication number: 20220302088
    Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.
    Type: Application
    Filed: November 29, 2021
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsien Yang, Hiroki Noguchi, Mahmut Sinangil, Yih Wang
  • Patent number: 11401542
    Abstract: An acoustically actuated droplet apparatus includes a first sound source, a second sound source, a thread, two fixed columns and at least one droplet transporter. The first sound source includes a first emitting surface. The second sound source includes a second emitting surface, wherein the second emitting surface and the first emitting surface are arranged opposite to each other. The thread is coaxially passed through and placed between the first sound source and the second sound source, wherein the thread is hydrophobic. The two fixed columns are connected to two ends of the thread, wherein the first sound source and the second sound source are placed between the two fixed columns. The droplet transporter includes a tubing, a droplet dispenser and a solution container, wherein the droplet dispenser is connected with the solution container by the tubing, and the droplet dispenser is placed near the thread.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 2, 2022
    Assignee: National Tsing Hua University
    Inventors: Pawel Lukasz Urban, Tzu-Hsien Yang