Patents by Inventor Tzu-Hsuan CHENG

Tzu-Hsuan CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096734
    Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tzu-Hsuan CHENG, Yong LIU, Liangbiao CHEN
  • Patent number: 11935452
    Abstract: An electronic circuit for operating with a display panel including touch sensors and fingerprint sensors is provided. The electronic circuit includes a first circuit, a second circuit, a third circuit, a first switch circuit and a control circuit. The first circuit generates display driving signals for driving the display panel. The second circuit receives fingerprint sensing signals from the fingerprint sensors. The third circuit determines a touch information according to touch sensing signals from the touch sensors. The first switch circuit includes a plurality of first switch units, each of the first switch units includes a first switch element and a second switch element. The control circuit controls the first switch circuit to transmit the display driving signals in a first time interval, controls the first switch circuit to transmit the fingerprint sensing signals in a second time interval, and controls the third circuit to receive the fingerprint sensing signals in a third time interval.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 19, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Huan-Teng Cheng, Ting-Hsuan Hung, Tzu-Wen Hsieh, Wei-Lun Shih, Huang-Chin Tang
  • Patent number: 11842942
    Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: December 12, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Liangbiao Chen, Yong Liu, Tzu-Hsuan Cheng, Stephen St. Germain, Roger Arbuthnot
  • Patent number: 11830784
    Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: November 28, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tzu-Hsuan Cheng, Yong Liu, Liangbiao Chen
  • Publication number: 20220208637
    Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block. Claims 3 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
    Type: Application
    Filed: March 18, 2022
    Publication date: June 30, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Liangbiao CHEN, Yong LIU, Tzu-Hsuan CHENG, Stephen ST. GERMAIN, Roger ARBUTHNOT
  • Patent number: 11282764
    Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Liangbiao Chen, Yong Liu, Tzu-Hsuan Cheng, Stephen St. Germain, Roger Arbuthnot
  • Publication number: 20210398874
    Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.
    Type: Application
    Filed: September 7, 2021
    Publication date: December 23, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tzu-Hsuan CHENG, Yong LIU, Liangbiao CHEN
  • Patent number: 11121055
    Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: September 14, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tzu-Hsuan Cheng, Yong Liu, Liangbiao Chen
  • Publication number: 20210249329
    Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 12, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Liangbiao CHEN, Yong LIU, Tzu-Hsuan CHENG, Stephen ST. GERMAIN, Roger ARBUTHNOT
  • Publication number: 20210217679
    Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 15, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tzu-Hsuan CHENG, Yong LIU, Liangbiao CHEN
  • Patent number: 10741644
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided. The electrode is electrically connected to the substrate through the via.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 11, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Shiau-Shi Lin, Tzu-Hsuan Cheng, Hsin-Chang Tsai
  • Patent number: 10056319
    Abstract: A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: August 21, 2018
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chia-Yen Lee, Hsin-Chang Tsai, Peng-Hsin Lee, Shiau-Shi Lin, Tzu-Hsuan Cheng
  • Publication number: 20180145018
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided.
    Type: Application
    Filed: November 22, 2016
    Publication date: May 24, 2018
    Inventors: Shiau-Shi LIN, Tzu-Hsuan CHENG, Hsin-Chang TSAI
  • Publication number: 20170317015
    Abstract: A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.
    Type: Application
    Filed: April 11, 2017
    Publication date: November 2, 2017
    Inventors: Chia-Yen LEE, Hsin-Chang TSAI, Peng-Hsin LEE, Shiau-Shi LIN, Tzu-Hsuan CHENG