Abstract: In at least one aspect, a method can include shaping a block of flexible spacer material. The method can include shaping a portion of the block of flexible spacer material to receive a solid metal block. The method can include coupling the solid metal block to the portion of the block of flexible spacer material.

Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.

Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block. Claims 3 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.

Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.

Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.

Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided. The electrode is electrically connected to the substrate through the via.

Abstract: A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided.

Abstract: A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.