Patents by Inventor Tzu Hsuan Lu

Tzu Hsuan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Photolithography alignment mark, mask and semiconductor wafer containing the same mark
    Patent number: 9024456
    Abstract: A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: May 5, 2015
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xiaosong Yang, Yibo Yan, Tzu Hsuan Lu
  • PHOTOLITHOGRAPHY ALIGNMENT MARK, MASK AND SEMICONDUCTOR WAFER CONTAINING THE SAME MARK
    Publication number: 20130075938
    Abstract: A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer.
    Type: Application
    Filed: December 16, 2011
    Publication date: March 28, 2013
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: XIAOSONG YANG, Yibo Yan, Tzu Hsuan Lu