Patents by Inventor Tzu-Hua LIN

Tzu-Hua LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978678
    Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: May 7, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 11942433
    Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jen-Fu Liu, Ming Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Tzu-Sung Huang
  • Publication number: 20240079483
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.
    Type: Application
    Filed: March 22, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hung LIN, I-Hsieh WONG, Tzu-Hua CHIU, Cheng-Yi PENG, Chia-Pin LIN
  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Publication number: 20240066392
    Abstract: A control assembly includes two controllers and a retractable and foldable mechanism, the retractable and foldable mechanism includes two retractable parts and a central part, and the two controllers are respectively movably connected to two opposite ends of the central part via the two retractable parts.
    Type: Application
    Filed: May 5, 2023
    Publication date: February 29, 2024
    Applicant: DEXIN CORP.
    Inventors: Ho Lung LU, Chin-Lung LIN, Tzu-Hua TSENG
  • Patent number: 9196595
    Abstract: The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 24, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Hua Chen, Tzu-Hua Lin, Kuan-Neng Chen, Yan-Pin Huang
  • Patent number: 9019808
    Abstract: A method for transmitting data stream includes the steps of analyzing a request to generate a transmitting command, calculating a data receiving ability of a receiving end when receiving the transferring command, calculating an I frame dividing rate, a P frame dividing rate, and a B frame dividing rate based on the data receiving ability, dividing an I frame, a P frame, and a B frame based on the I frame dividing rate, the P frame dividing rate, and the B frame dividing rate to generate a plurality of I frame segments, P frame segments, and B frame segments, transmitting the I frame segments, P frame segments, and B frame segments of the data stream to the receiving end in turn base on the data receiving ability.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: April 28, 2015
    Assignee: Institute for Information Industry
    Inventors: Chung-Ming Huang, Yuan-Tse Yu, Tzu-Hua Lin
  • Publication number: 20140239494
    Abstract: The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 28, 2014
    Inventors: Kuo-Hua CHEN, Tzu-Hua LIN, Kuan-Neng CHEN, Yan-Pin HUANG
  • Publication number: 20140146658
    Abstract: A method for transmitting data stream includes the steps of analyzing a request to generate a transmitting command, calculating a data receiving ability of a receiving end when receiving the transferring command, calculating an I frame dividing rate, a P frame dividing rate, and a B frame dividing rate based on the data receiving ability, dividing an I frame, a P frame, and a B frame based on the I frame dividing rate, the P frame dividing rate, and the B frame dividing rate to generate a plurality of I frame segments, P frame segments, and B frame segments, transmitting the I frame segments, P frame segments, and B frame segments of the data stream to the receiving end in turn base on the data receiving ability.
    Type: Application
    Filed: December 17, 2012
    Publication date: May 29, 2014
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Chung-Ming HUANG, Yuan-Tse YU, Tzu-Hua LIN