Patents by Inventor Tzu-Jen Chou

Tzu-Jen Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7407601
    Abstract: A slurry system for a chemical mechanical polishing (CMP) process and a method for using the same wherein the slurry system includes an aqueous dispersion comprising at least abrasive polymer containing particles in an alkaline solution having a pH of less than about 9.5; and wherein the method includes providing a semiconductor wafer process surface including a oxide containing material and metal filled semiconductor features; providing the system; and, polishing in a CMP process the semiconductor wafer process surface using the slurry system to remove at least a portion of the oxide containing material and the metal comprising the metal filled semiconductor features.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: August 5, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Shen-Nan Lee, Ying-Ho Chen, Syun-Ming Jang, Tzu-Jen Chou
  • Patent number: 7253524
    Abstract: A semiconductor substrate has a first copper layer, on which an etch stop layer and a dielectric layer are successively formed. A second copper layer penetrates the dielectric layer and the etch stop layer to electrically connect to the first metal layer. The etch stop layer has a dielectric constant smaller than 3.5, and the dielectric layer has a dielectric constant smaller than 3.0.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: August 7, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhen-Cheng Wu, Tzu-Jen Chou, Weng Chang, Yung-Cheng Lu, Syun-Ming Jang, Mong-Song Liang
  • Patent number: 6924238
    Abstract: A new method and structure is provided for the polishing of the surface of a layer of low-k dielectric material. Low-k dielectric material of low density and relatively high porosity is combined with low-k dielectric material of high density and low porosity whereby the latter high density layer is, prior to polishing of the combined layers, deposited over the former low density layer. Polishing of the combined layers removes flaking of the polished low-k layers of dielectric. This method can further be extended by forming conductive interconnects through the layers of dielectric, prior to the layer of dielectric.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: August 2, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Jen Chou, Syun-Ming Jang, Ying-Ho Chen, Shen-Nan Lee
  • Patent number: 6919276
    Abstract: A CMP process for selectively polishing an overlying material layer with an underlying layer comprising at least one material in a semiconductor device fabrication process including providing a semiconductor wafer process surface including a first material layer overlying a second layer including one material; mixing at least two slurry mixtures including a first CMP slurry formulation optimized for removing the first material layer and a second CMP slurry formulation optimized for removing the at least a second layer to form a slurry formulation mixture; and, carrying out a CMP process using the slurry formulation mixture to remove the first material layer and at least a portion of the at least a second layer.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: July 19, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Shen-Nan Lee, Ying-Ho Chen, Syun-Ming Jang, Tzu-Jen Chou, Jin-Yiing Song
  • Publication number: 20050110153
    Abstract: A semiconductor substrate has a first copper layer, on which an etch stop layer and a dielectric layer are successively formed. A second copper layer penetrates the dielectric layer and the etch stop layer to electrically connect to the first metal layer. The etch stop layer has a dielectric constant smaller than 3.5, and the dielectric layer has a dielectric constant smaller than 3.0.
    Type: Application
    Filed: March 10, 2004
    Publication date: May 26, 2005
    Inventors: Zhen-Cheng Wu, Tzu-Jen Chou, Weng Chang, Yung-Cheng Lu, Syun-Ming Jang, Mong-Song Liang
  • Publication number: 20040248426
    Abstract: A new method and structure is provided for the polishing of the surface of a layer of low-k dielectric material. Low-k dielectric material of low density and relatively high porosity is combined with low-k dielectric material of high density and low porosity whereby the latter high density layer is, prior to polishing of the combined layers, deposited over the former low density layer. Polishing of the combined layers removes flaking of the polished low-k layers of dielectric. This method can further be extended by forming conductive interconnects through the layers of dielectric, prior to the layer of dielectric.
    Type: Application
    Filed: June 5, 2003
    Publication date: December 9, 2004
    Applicant: Taiwan Semicondutor Manufacturing Co.
    Inventors: Tzu-Jen Chou, Syun-Ming Jang, Ying-Ho Chen, Shen-Nan Lee
  • Publication number: 20040226918
    Abstract: A slurry system for a chemical mechanical polishing (CMP) process and a method for using the same wherein the slurry system includes an aqueous dispersion comprising at least abrasive polymer containing particles in an alkaline solution having a pH of less than about 9.5; and wherein the method includes providing a semiconductor wafer process surface including a oxide containing material and metal filled semiconductor features; providing the system; and, polishing in a CMP process the semiconductor wafer process surface using the slurry system to remove at least a portion of the oxide containing material and the metal comprising the metal filled semiconductor features.
    Type: Application
    Filed: April 24, 2003
    Publication date: November 18, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shen-Nan Lee, Ying-Ho Chen, Syun-Ming Jang, Tzu-Jen Chou
  • Publication number: 20040214442
    Abstract: A CMP process for selectively polishing an overlying material layer with an underlying layer comprising at least one material in a semiconductor device fabrication process including providing a semiconductor wafer process surface including a first material layer overlying a second layer including one material; mixing at least two slurry mixtures including a first CMP slurry formulation optimized for removing the first material layer and a second CMP slurry formulation optimized for removing the at least a second layer to form a slurry formulation mixture; and, carrying out a CMP process using the slurry formulation mixture to remove the first material layer and at least a portion of the at least a second layer.
    Type: Application
    Filed: April 24, 2003
    Publication date: October 28, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shen-Nan Lee, Ying-Ho Chen, Syun-Ming Jang, Tzu-Jen Chou, Jin-Yiing Song