Abstract: The present disclosure provides a matrix device and an operation method thereof. The matrix device includes a transpose circuit and a memory. The transpose circuit is configured to receive a first element string representing a native matrix from a matrix source, wherein all elements in the native matrix are arranged in the first element string in one of a “row-major manner” and a “column-major manner”. The transpose circuit transposes the first element string into a second element string, wherein the second element string is equivalent to an element string in which all elements of the native matrix are arranged in another one of the “row-major manner” and the “column-major manner”. The memory is coupled to the transpose circuit to receive the second element string.

Abstract: An alert method and an alert system thereof. The alert method includes: detecting, by a turn detector installed on a steering wheel, a first turn and a second turn of the steering wheel in a predetermined period; generating, by a controller, a first alert signal based on the first and second turns; and when receiving the first alert signal, generating, by an alert device, a first alert message.

Abstract: An alert method and an alert system thereof. The alert method includes: detecting, by a turn detector installed on a steering wheel, a first turn and a second turn of the steering wheel in a predetermined period; generating, by a controller, a first alert signal based on the first and second turns; and when receiving the first alert signal, generating, by an alert device, a first alert message.

Abstract: Motherboards and graphics processing systems incorporating an integrated physics engine are disclosed. A proposed motherboard includes an integrated physics engine (IPE) including a north bridge circuit and a physics computing circuit; and a south bridge circuit coupled to the north bridge circuit.

Abstract: Motherboards with multiple integrated graphics processors (IGPs) for performing graphics processing operations are disclosed. A proposed motherboard includes a first integrated graphics processor (IGP) having a first north bridge circuit and a first graphics processing circuit; at least one second IGP, each having a second north bridge circuit and a second graphics processing circuit; and a south bridge circuit coupled to the first north bridge circuit.

Abstract: A switching fabric capable of supporting high bandwidth switching operations is disclosed. In one aspect, multiple switching chips and multiple links thereto are used to provide a high bandwidth switching fabric. In another aspect, payload data is transmitted following grant of its previously transmitted corresponding request. In yet another aspect, the switching fabric operates in a pipelined manner.

Abstract: A switching fabric capable of supporting high bandwidth switching operations is disclosed. In one aspect, multiple switching chips and multiple links thereto are used to provide a high bandwidth switching fabric. In another aspect, payload data is transmitted following grant of its previously transmitted corresponding request. In yet another aspect, the switching fabric operates in a pipelined manner.

Abstract: An improved approach for applying flow control within a switch system is disclosed. The improved approach makes use of scheduling operations performed by the switch system to implement receive-side flow control. Transmit-side flow control is independently provided. The improved approach of the invention enables the switch system to provide flow control in a bandwidth efficient manner.

Abstract: Efficient techniques for processing multicast requests in a switch system are disclosed. The efficient techniques lead to substantial reduction in switch system bandwidth consumption while processing multicast requests. In one embodiment, a multicast queue is used to hold multicast blocks of data (e.g., cells) that are to be switched, and duplication of the blocks of data for delivery to multiple destinations (e.g., ports) is performed by a switch device (e.g., crossbar switch) as opposed to storage queues or repeated transfers from storage queues to the switch device.