Abstract: A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.

Abstract: A device includes memory cells, reference memory cells, and a sensing unit. The reference memory cells are configured to store first bit data, second bit data, third bit data, and fourth bit data, in which the first bit data and the fourth bit data are configured to be a high logic state, and the second bit data and the third bit data are configured to be a low logic state. The sensing unit is configured to read bit data stored in one of the memory cells according to the first bit data, the second bit data, the third bit data, and the fourth bit data.

Abstract: A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.

Abstract: A device includes memory cells, reference memory cells, and a sensing unit. The reference memory cells are configured to store first bit data, second bit data, third bit data, and fourth bit data, in which the first bit data and the fourth bit data are configured to be a high logic state, and the second bit data and the third bit data are configured to be a low logic state. The sensing unit is configured to read bit data stored in one of the memory cells according to the first bit data, the second bit data, the third bit data, and the fourth bit data.

Abstract: A memory array includes a first memory cell and a second memory cell aligned along a column direction. Each of the first memory cell and the second memory cell includes a pair of cross-coupled inverters, a first switch on a first side, along the column direction, of the pair of cross-coupled inverters, a second switch aligned with the first switch along the column direction, on a second side of the pair of cross-coupled inverters opposing to the first side, a third switch on the first side of the pair of cross-coupled inverters, and a fourth switch aligned with the third switch along the column direction, on the second side of the pair of cross-coupled inverters. The memory array also includes a first data line, a first complementary data line, a second data line and a second complementary data line.

Abstract: An electronic device is disclosed that includes n memory cells, a replica memory array, and a sensing unit. Each of the n memory cells stores bit data, in which n is a positive integer. The replica memory array includes a first reference memory cell having a high logic state, a second reference memory cell having a low logic state, n?1 first pseudo reference memory cells having the low logic state, and n?1 second pseudo reference memory cells having the high logic state. The first reference memory cell and the n?1 first pseudo reference memory cells generate a first signal, and the second reference memory cell and the n?1 second pseudo reference memory cells generate a second signal. The sensing unit determines a logic state of the bit data of one of the n memory cells according to the first signal and the second signal.

Abstract: An electronic device is disclosed that includes n memory cells, a replica memory array, and a sensing unit. Each of the n memory cells stores bit data, in which n is a positive integer. The replica memory array includes a first reference memory cell having a high logic state, a second reference memory cell having a low logic state, n?1 first pseudo reference memory cells having the low logic state, and n?1 second pseudo reference memory cells having the high logic state. The first reference memory cell and the n?1 first pseudo reference memory cells generate a first signal, and the second reference memory cell and the n?1 second pseudo reference memory cells generate a second signal. The sensing unit determines a logic state of the bit data of one of the n memory cells according to the first signal and the second signal.

Abstract: A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.

Abstract: A three dimensional dual-port bit cell generally comprises a first portion of a latch disposed on a first tier, wherein the first portion includes a plurality of first port elements. A second portion of the latch is disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a plurality of second port elements.

Abstract: A memory array includes a first memory cell and a second memory cell aligned along a column direction. Each of the first memory cell and the second memory cell includes a pair of cross-coupled inverters, a first switch on a first side, along the column direction, of the pair of cross-coupled inverters, a second switch aligned with the first switch along the column direction, on a second side of the pair of cross-coupled inverters opposing to the first side, a third switch on the first side of the pair of cross-coupled inverters, and a fourth switch aligned with the third switch along the column direction, on the second side of the pair of cross-coupled inverters. The memory array also includes a first data line, a first complementary data line, a second data line and a second complementary data line.

Abstract: A memory cell includes a first, second, and third columns of devices. The first column of devices includes a first pull-down transistor, a second pull-down transistor, a first switch, and a second switch. The second column of devices includes a third pull-down transistor, a fourth pull-down transistor, a third switch, and a fourth switch. The third column of devices includes a first pull-up transistor, and a second pull-up transistor. The first pull-up transistor, the first pull-down transistor, and the third pull-down transistor are connected as a first inverter, and the second pull-up transistor, the second pull-down transistor, and the fourth pull-down transistor are connected as a second inverter. The first inverter and the second inverter are cross-coupled. The first switch, the second switch, the third switch, and the fourth switch are coupled with output terminals of the first and second inverters.

Abstract: A three dimensional dual-port bit cell generally comprises a first portion of a latch disposed on a first tier, wherein the first portion includes a plurality of first port elements. A second portion of the latch is disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a plurality of second port elements.

Abstract: A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.

Abstract: A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.

Abstract: A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.

Abstract: A memory cell includes a first, second, and third columns of devices. The first column of devices includes a first pull-down transistor, a second pull-down transistor, a first switch, and a second switch. The second column of devices includes a third pull-down transistor, a fourth pull-down transistor, a third switch, and a fourth switch. The third column of devices includes a first pull-up transistor, and a second pull-up transistor. The first pull-up transistor, the first pull-down transistor, and the third pull-down transistor are connected as a first inverter, and the second pull-up transistor, the second pull-down transistor, and the fourth pull-down transistor are connected as a second inverter. The first inverter and the second inverter are cross-coupled. The first switch, the second switch, the third switch, and the fourth switch are coupled with output terminals of the first and second inverters.

Abstract: A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.

Abstract: A semiconductor memory includes first and second word lines. A first bit cell of a first type is coupled to a first one of a plurality of bit lines and has a first layout in which the first bit cell of the first type is coupled to the first word line with a first number of vias and to the second word line with a second number of vias. A first bit cell of a second type is coupled to a second one of the plurality of bit lines and has a second layout in which the first bit cell of the second type is coupled to the first word line with a third number of vias and to the second word line with a fourth number of vias. A load on the first word line is approximately equal to a load on the second word line.

Abstract: A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.

Abstract: A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.