Patents by Inventor Tzu-Li Tseng

Tzu-Li Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11289366
    Abstract: A method of manufacturing a semiconductor structure includes the following operations. A buffer layer is formed over a substrate. A first top hard mask is formed on the buffer layer, in which the first top hard mask has a first trench to expose a first portion of the buffer layer. A spacer layer is formed to cover a sidewall of the first trench and an upper surface of the first top hard mask and the first portion of the buffer layer to form a second trench over the first portion. The top portion and the bottom portion are etched to form a thinned top portion and a thinned bottom portion. A second top hard mask is formed in the second trench. The thinned top portion and the vertical portion of the spacer layer are removed.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: March 29, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ying-Cheng Chuang, Tzu-Li Tseng, Tsung-Cheng Chen
  • Publication number: 20190057870
    Abstract: A method of forming fine line patterns of semiconductor devices includes: forming a plurality of linear core structures on at least one hard mask layer disposed on a target layer; forming first spacers on sidewalls of the linear core structures; removing the linear core structures; forming second spacers on sidewalls of the first spacers; etching exposed portions of the hard mask layer exposed by the first spacers and the second spacers; and removing the first spacers and the second spacers.
    Type: Application
    Filed: August 17, 2017
    Publication date: February 21, 2019
    Inventors: Shing-Yih SHIH, Chih-Ching LIN, Tzu-Li TSENG
  • Patent number: 10147611
    Abstract: The present disclosure provides a method for preparing semiconductor structures. The method includes the following steps: A substrate is provided. A plurality of first core features spaced apart from each other is formed over the substrate. A spacer layer is formed over the first core features, and the spacer layer is formed to cover sidewalls and top surfaces of each first core feature. A plurality of second core features is formed over the substrate, and portions of the spacer layer are exposed through the second core features. A densification treatment is performed on the second core features, and the spacer layer is removed to form a plurality of openings between the first core features and the second core features.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 4, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Cheng-Wei Wang, Tzu-Li Tseng