Patents by Inventor Tzu-Liang Lee

Tzu-Liang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6967130
    Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: November 22, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Chun Chen, Tzu-Liang Lee, Shih-Chang Chen
  • Publication number: 20040259341
    Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.
    Type: Application
    Filed: June 20, 2003
    Publication date: December 23, 2004
    Applicant: Taiwan Semicondutor Manufacturing Co.
    Inventors: Chi-Chun Chen, Tzu-Liang Lee, Shih-Chang Chen