Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.

Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

Abstract: A device structure according to the present disclosure may include a first die having a first substrate and a first interconnect structure, a second die having a second substrate and a second interconnect structure, and a third die having a third interconnect structure and a third substrate. The first interconnect structure is bonded to the second substrate via a first plurality of bonding layers. The second interconnect structure is bonded to the third interconnect structure via a second plurality of bonding layers. The third substrate includes a plurality of photodiodes and a first transistor. The second die includes a second transistor having a source connected to a drain of the first transistor, a third transistor having a gate connected to drain of the first transistor and the source of the second transistor, and a fourth transistor having a drain connected to the source of the third transistor.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including first chip and a second chip. The first chip includes a first substrate, a plurality of photodetectors disposed in the first substrate, a first interconnect structure disposed on a front side of the first substrate, and a first bond structure disposed on the first interconnect structure. The second chip underlies the first chip. The second chip includes a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bond structure disposed on the second interconnect structure. A first bonding interface is disposed between the second bond structure and the first bond structure. The second interconnect structure is electrically coupled to the first interconnect structure by way of the first and second bond structures.

Abstract: A multi-threads tracking method, a multi-threads tracking system for an operating system and an electronic device using the same are provided. The multi-threads tracking method of the operating system includes the following steps. At least two message queue access events among two threads and one message queue are intercepted. A thread identification, a process identification, an input value and a return value of each of the message queue access events are recorded. Based on a determination of a relationship among the thread identifications, the process identifications, the input values, and the return values of the message queue access events, an In-Process dependency among the threads and the message queue is established.

Abstract: The disclosure provides a controller, a method for adjusting packet flow rule, and a network communication system. The method includes: receiving, by a controller, a health status of a first port and a health status of a second port of each of a plurality of hosts in the network communication system; adjusting a packet flow rule of each of the hosts based on the health status of the first port and the health status of the second port of each of the hosts; and transmitting the adjusted packet flow rule of each of the hosts to each of the corresponding hosts to control each of the hosts to transceive a packet according to the corresponding packet flow rule.

Abstract: A virtual local area network configuration system, a method and a computer program product thereof are provided. The virtual local area network configuration system includes physical machines running virtual machines, Ethernet switches and a network controller. The network controller deploys VLAN groups according to the physical machines and the virtual machines, creates virtual topologies corresponding to the VLAN groups and assigns VLAN IDs to the VLAN groups, wherein at least two VLAN groups among the VLAN groups have the same VLAN ID.

Abstract: The disclosure provides a controller, a method for adjusting packet flow rule, and a network communication system. The method includes: receiving, by a controller, a health status of a first port and a health status of a second port of each of a plurality of hosts in the network communication system; adjusting a packet flow rule of each of the hosts based on the health status of the first port and the health status of the second port of each of the hosts; and transmitting the adjusted packet flow rule of each of the hosts to each of the corresponding hosts to control each of the hosts to transceive a packet according to the corresponding packet flow rule.

Abstract: A network communication method, a system and a controller of PCIe and Ethernet hybrid networks are provided. In one example of the network communication method, a packet is transmitted or received via a network interface (NIC). The packet is transmitted via an Ethernet over PCIe (EoP) port by adopting a PCIe based EoP architecture based on a PCIe bus for an intra-rack transmission, and the packet is transmitted via an Ethernet port for an inter-rack transmission. If the transmitted packet belongs to a broadcast packet, the network interface receiving the packet discards the packet or transmits the packet to the controller without re-broadcasting the packet again.

Abstract: A network communication method, a system and a controller of PCIe and Ethernet hybrid networks are provided. In one example of the network communication method, a packet is transmitted or received via a network interface (NIC). The packet is transmitted via an Ethernet over PCIe (EoP) port by adopting a PCIe based EoP architecture based on a PCIe bus for an intra-rack transmission, and the packet is transmitted via an Ethernet port for an inter-rack transmission. If the transmitted packet belongs to a broadcast packet, the network interface receiving the packet discards the packet or transmits the packet to the controller without re-broadcasting the packet again.

Abstract: A virtual local area network configuration system, a method and a computer program product thereof are provided. The virtual local area network configuration system includes physical machines running virtual machines, Ethernet switches and a network controller. The network controller deploys VLAN groups according to the physical machines and the virtual machines, creates virtual topologies corresponding to the VLAN groups and assigns VLAN IDs to the VLAN groups, wherein at least two VLAN groups among the VLAN groups have the same VLAN ID.