Abstract: The present disclosure discloses an image processing circuit having output timing adjustment mechanism. An image enhancement circuit performs image enhancement on an input image to generate an enhanced image. A first image processing path and a second image processing path respectively perform processing on the enhanced image having a first timing and the enhanced image having a second timing to generate a first output image and a second output image. A timing control circuit adjusts the timing of the enhanced image according to requirements of the first image processing path and the second image processing path to generate the enhanced image having the first timing and the enhanced image having the second timing. A first image output interface outputs the first output image. A second image output interface outputs the second output image.

Abstract: A control signal transmission circuit and a control signal receiving circuit for an audio/video interface are provided. The control signal transmission circuit includes an audio/video interface encoder, a signal packaging circuit and a data allocator. The audio/video interface encoder is configured to receive an audio packet and supports a user-defined packet format. The signal packaging circuit is configured to receive a first control signal and package the first control signal into a control data packet according to the user-defined packet format. The data allocator is configured to receive a video data and a second control signal and to mix the second control signal and the video data to generate a mixed data packet. The audio/video interface encoder packages the control data packet, the mixed data packet and the audio packet according to an audio/video transmission protocol to generate an audio/video and control data.

Abstract: A signal processing method for maintaining a signal relative relationship and an electronic device thereof are provided. The signal processing method includes: detecting that a current input period of a vertical synchronization signal changes relative to a previous input period; determining whether a frequency difference between a pulse width modulation signal and the vertical synchronization signal is within an acceptable range, and when the frequency difference is not within the acceptable range, performing a frequency adjustment stage to adjust a period of the pulse width modulation signal to be close to the current input period; selectively performing a phase adjustment stage to adjust a phase of the pulse width modulation signal to a phase of the vertical synchronization signal; and maintaining a relative phase relationship between the pulse width modulation signal and the vertical synchronization signal.

Abstract: A control signal transmission circuit and a control signal receiving circuit for an audio/video interface are provided. The control signal transmission circuit includes an audio/video interface encoder, a signal packaging circuit and a data allocator. The audio/video interface encoder is configured to receive an audio packet and supports a user-defined packet format. The signal packaging circuit is configured to receive a first control signal and package the first control signal into a control data packet according to the user-defined packet format. The data allocator is configured to receive a video data and a second control signal and to mix the second control signal and the video data to generate a mixed data packet. The audio/video interface encoder packages the control data packet, the mixed data packet and the audio packet according to an audio/video transmission protocol to generate an audio/video and control data.

Abstract: A signal processing method for maintaining a signal relative relationship and an electronic device thereof are provided. The signal processing method includes: detecting that a current input period of a vertical synchronization signal changes relative to a previous input period; determining whether a frequency difference between a pulse width modulation signal and the vertical synchronization signal is within an acceptable range, and when the frequency difference is not within the acceptable range, performing a frequency adjustment stage to adjust a period of the pulse width modulation signal to be close to the current input period; selectively performing a phase adjustment stage to adjust a phase of the pulse width modulation signal to a phase of the vertical synchronization signal; and maintaining a relative phase relationship between the pulse width modulation signal and the vertical synchronization signal.