Patents by Inventor Tzu-Ming Huang

Tzu-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128666
    Abstract: A motherboard includes a circuit board and a connector mounted on the circuit board. The connector comprises a socket and a latch pivotally mounted on one end of the socket. The latch comprises a body, a pressing member connected to one side of the body and extending outward from one side of the body to the outside of the socket, exposing an area from a side of the interface card for finger pressing. The supporting member is connected to another side of the body, and when the pressing member is pressed, it drives the body to pivot and causes the pushing portion to lift the interface card, and the supporting member stop the body from pivoting by resting against the circuit board.
    Type: Application
    Filed: September 22, 2023
    Publication date: April 18, 2024
    Inventors: CHIH-MING LAI, YUNG-SHUN KAO, TZU-HSIANG HUANG
  • Patent number: 11924444
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 9748377
    Abstract: A semiconductor device includes a gate structure, a source region and a drain region. The source region and the drain region are on opposite sides of the gate structure. The source region includes a first region of a first conductivity type and a second region of a second conductivity type. The second conductivity type is opposite to the first conductivity type. The first region is between the second region and the gate structure. The second region includes at least one projection protruding into the first region and toward the gate structure.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: August 29, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Ming Huang, Shen-Ping Wang, Lieh-Chuan Chen, Chih-Heng Shen, Po-Tao Chu
  • Patent number: 9666511
    Abstract: A semiconductor package having a lead frame over which a first device and a second device are spaced is provided. The lead frame includes a die pad upon which a first chip and a second chip are spaced and bonded. The first chip includes the first device, which has a first operating voltage. The second chip includes the second device, which has a second operating voltage greater than the first operating voltage. A dielectric layer is arranged between the die pad and the second device. A method for manufacturing the semiconductor package is also provided.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Ming Huang, Shen-Ping Wang, Lieh-Chuan Chen, Po-Tao Chu
  • Publication number: 20160211203
    Abstract: A semiconductor package having a lead frame over which a first device and a second device are spaced is provided. The lead frame includes a die pad upon which a first chip and a second chip are spaced and bonded. The first chip includes the first device, which has a first operating voltage. The second chip includes the second device, which has a second operating voltage greater than the first operating voltage. A dielectric layer is arranged between the die pad and the second device. A method for manufacturing the semiconductor package is also provided.
    Type: Application
    Filed: January 15, 2015
    Publication date: July 21, 2016
    Inventors: Tzu-Ming Huang, Sheng-Ping Wang, Lieh-Chuan Chen, Po-Tao Chu
  • Publication number: 20160043215
    Abstract: A semiconductor device includes a gate structure, a source region and a drain region. The source region and the drain region are on opposite sides of the gate structure. The source region includes a first region of a first conductivity type and a second region of a second conductivity type. The second conductivity type is opposite to the first conductivity type. The first region is between the second region and the gate structure. The second region includes at least one projection protruding into the first region and toward the gate structure.
    Type: Application
    Filed: October 19, 2015
    Publication date: February 11, 2016
    Inventors: Tzu-Ming HUANG, Shen-Ping WANG, Lieh-Chuan CHEN, Chih-Heng SHEN, Po-Tao CHU
  • Patent number: 9184282
    Abstract: Embodiments for the present disclosure include a semiconductor device, an ultra-high voltage (UHV) laterally-diffused metal-oxide-semiconductor (LDMOS) transistor, and methods of forming the same. An embodiment includes a first well region of a first conductivity type in a top surface of a substrate, and a second well region of a second conductivity type in the top surface of the substrate. The second well region laterally separated from the first well region by a portion of the substrate. The embodiment further includes a third region of the second conductivity type in the first well region, and a first field oxide region in the first well region, a second field oxide region in the second well region, the second field oxide region having a second bottom surface, and the first field oxide region having a first bottom surface lower than the second bottom surface and on and directly contacting the third region.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ming Huang, Chia-Chia Kan, Shen-Ping Wang, Lieh-Chuan Chen, Po-Tao Chu
  • Patent number: 9166046
    Abstract: A semiconductor device includes a gate structure, and a source region and a drain region on opposite sides of the gate structure. The source region comprises a first region of a first conductivity type, and a second region of a second conductivity type, the second conductivity type opposite to the first conductivity type. The first region is arranged between the second region and the gate structure. The second region comprises at least one projection protruding into the first region and toward the gate structure.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: October 20, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Ming Huang, Shen-Ping Wang, Lieh-Chuan Chen, Chih-Heng Shen, Po-Tao Chu
  • Publication number: 20150236149
    Abstract: A semiconductor device includes a gate structure, and a source region and a drain region on opposite sides of the gate structure. The source region comprises a first region of a first conductivity type, and a second region of a second conductivity type, the second conductivity type opposite to the first conductivity type. The first region is arranged between the second region and the gate structure. The second region comprises at least one projection protruding into the first region and toward the gate structure.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Ming HUANG, Shen-Ping WANG, Lieh-Chuan CHEN, Chih-Heng SHEN, Po-Tao CHU
  • Publication number: 20150076307
    Abstract: A holder assembly for supporting a displaying device is disclosed in the present invention. The holder assembly includes a base, a brace and a supporting arm. An end of the brace is connected to the base, and a sphere is disposed on the other end of the brace. An end of the supporting arm is connected to the displaying device, and a pivot portion is disposed on the other end of the supporting arm. The pivot portion corresponds to the sphere, and the sphere is rotatably disposed on the pivot portion. Comparing to the prior art, the present invention has preferable convenience.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: Top Victory Investments Ltd.
    Inventors: Tsung-Ping Tsai, Tzu-Ming Huang
  • Publication number: 20150041891
    Abstract: Embodiments for the present disclosure include a semiconductor device, an ultra-high voltage (UHV) laterally-diffused metal-oxide-semiconductor (LDMOS) transistor, and methods of forming the same. An embodiment includes a first well region of a first conductivity type in a top surface of a substrate, and a second well region of a second conductivity type in the top surface of the substrate. The second well region laterally separated from the first well region by a portion of the substrate. The embodiment further includes a third region of the second conductivity type in the first well region, and a first field oxide region in the first well region, a second field oxide region in the second well region, the second field oxide region having a second bottom surface, and the first field oxide region having a first bottom surface lower than the second bottom surface and on and directly contacting the third region.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ming Huang, Chia-Chia Kan, Shen-Ping Wang, Lieh-Chuan Chen, Po-Tao Chu
  • Publication number: 20100231185
    Abstract: A power conversion assembly includes a conversion box, a conversion lead and a plurality of adapter plugs. The conversion box has a power regulation circuit, a variable switch, a power input port, a power output port and at least a interface port. The variable switch, the power input port, the power output port and the at least one interface port are connected with the power regulation circuit. When the conversion box is connected with the power adapter to obtain a DC power, a DC power with a different voltage can be sent out by the switching of the variable switch and the regulation of the power regulation circuit. One end of the conversion lead is used to receive the regulated DC power from the conversion box. The other end of the conversion lead can be replaced with the adapter plug having different specification to supply power to different power-requiring equipment.
    Type: Application
    Filed: December 10, 2009
    Publication date: September 16, 2010
    Applicant: ACBEL POLYTECH INC.
    Inventors: Tung-Yao YU, Sung-Po YANG, Tzu-Ming HUANG
  • Patent number: 7264170
    Abstract: An input device. The input device may be coupled to an electronic device. The input device comprises a control capable of being moved to n activation points to respectively activate input functions, wherein n is an integer larger than or equal to ten. When activated, the input functions respectively enable n digits to be input to the electronic device.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: September 4, 2007
    Assignee: Inventec Appliances Corporation
    Inventors: Pin-Chia Lee, Tzu-Ming Huang
  • Publication number: 20050274785
    Abstract: An input device. The input device may be coupled to an electronic device. The input device comprises a control capable of being moved to n activation points to respectively activate input functions, wherein n is an integer larger than or equal to ten. When activated, the input functions respectively enable n digits to be input to the electronic device.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 15, 2005
    Inventors: Pin-Chia Lee, Tzu-Ming Huang
  • Patent number: D816569
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 1, 2018
    Inventor: Tzu-Ming Huang
  • Patent number: D1002459
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: October 24, 2023
    Inventor: Tzu-Ming Huang