Abstract: This disclosure relates to a polishing composition that includes an abrasive, at least two pH adjusters, a barrier film removal rate enhancer, a low-k removal rate inhibitor, and an azole-containing corrosion inhibitor. This disclosure also features a method of using the polishing composition to polish a substrate containing copper and silicon oxide.

Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.

Abstract: The present invention discloses a storage device and a circuit element switching method thereof. The storage device includes: a plurality of memory modules, wherein each of the plurality of memory modules includes a plurality of chip enable terminals; a memory control unit that includes a plurality of bank selection terminals; and a switch module that is coupled between the plurality of memory modules and the memory control unit, and utilized for dispersedly coupling the plurality of bank selection terminals to the plurality of chip enable terminals of each of the plurality of memory modules. The circuit element switching method applied to the storage device includes: providing a memory control unit including a plurality of bank selection terminals; and dispersedly coupling the plurality of bank selection terminals to a plurality of chip enable terminals of each of the plurality of memory modules.