Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract: In doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar semiconductor body. The first ion implant has a first implant energy and a first implant angle. A second ion implant is performed in the same region of the non-planar semiconductor body. The second ion implant has a second implant energy and a second implant angle. The first implant energy may be different from the second implant energy. Additionally, the first implant angle may be different from the second implant angle.

Abstract: In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different.

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched to expose a first region of the fin. A portion of the first region is then doped with a dopant.

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract: In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different.

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract: In doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar semiconductor body. The first ion implant has a first implant energy and a first implant angle. A second ion implant is performed in the same region of the non-planar semiconductor body. The second ion implant has a second implant energy and a second implant angle. The first implant energy may be different from the second implant energy. Additionally, the first implant angle may be different from the second implant angle.

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched to expose a first region of the fin. A portion of the first region is then doped with a dopant.

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract: A memory unit comprising a gate electrode, a gate dielectric under said gate electrode, an active area and a metal-semiconductor compound layer is provided. The active area comprises a first source/drain region, a second source/drain region, a normal field channel region formed under said gate electrode, a fringing field channel region formed between said first source/drain region and said normal field channel region, a pocket implantation region formed under the fringing or normal field channel regions and an extension doping region formed between said second source/drain region and said normal field channel region. The metal-semiconductor compound layer is formed over said gate electrode, first source/drain region and second source/drain region.

Abstract: A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or a first bit line, a drain region coupled to a drain line or a second bit line, a first spacer between the source region and the gate electrode and a second spacer between the drain region and the gate electrode. When a first-bit program operation is performed on the memory unit, a switch-on signal is applied to the gate, a programming signal is applied to the source region and the drain region is switched to ground. As the memory unit is activated, the carriers are injected and stored in a first spacer, thus represents a first bit in the memory unit.

Abstract: A memory unit comprising a gate electrode, a gate dielectric under said gate electrode, an active area and a metal-semiconductor compound layer is provided. The active area comprises a first source/drain region, a second source/drain region, a normal field channel region formed under said gate electrode, a fringing field channel region formed between said first source/drain region and said normal field channel region, and an extension doping region formed between said second source/drain region and said normal field channel region. The metal-semiconductor compound layer is formed over said gate electrode, first source/drain region and second source/drain region.

Abstract: A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or a first bit line, a drain region coupled to a drain line or a second bit line, a first spacer between the source region and the gate electrode and a second spacer between the drain region and the gate electrode. When a first-bit program operation is performed on the memory unit, a switch-on signal is applied to the gate, a programming signal is applied to the source region and the drain region is switched to ground. As the memory unit is activated, the carriers are injected and stored in a first spacer, thus represents a first bit in the memory unit.

Abstract: The present invention discloses a method for simultaneously removing from a silicon surface polymeric films and damaged silicon layers by exposing the surface to a cleaning solution that contains amine or ethanolamine for a length of time that is sufficient to remove all such unwanted materials. The method is effective in cleaning away damaged silicon layers having a thickness between about 20 Å and about 60 Å in a period of time between about 2 minutes and about 20 minutes. In a preferred embodiment, the cleaning solution is a water solution of ethanolamine and gallic acid.

Abstract: A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen.

Abstract: A method for forming self-aligned contact (SAC) is disclosed to improve device reliability. The method includes forming a dielectric liner over the contact opening before the contact plug is filled in. Optional contact implantation before and after the liner formation can be added to enhance the doping profile of the device.

Abstract: A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

Abstract: A method for making self-aligned contacts on a semiconductor substrate using a hard mask. After the transistor is formed, a blanket insulating layer is formed on said semiconductor substrate. A hard mask having openings on the blanket insulating layer is formed over the insulating layer. The openings overlay the source/drain region and part of the gate electrode structure. Using the patterned hard mask, the insulating layer is etched to the gate electrode protecting layer. Then self-aligned contacts is completed by etching the insulating layer to expose the source/drain regions using the gate electrode protecting layer and the insulating sidewall spacers as the mask.