Abstract: The present disclosure provides a semiconductor structure that includes a substrate having devices formed thereon and an interconnect structure electrically coupling the devices into an integrated circuit; a passivation structure formed on the interconnect structure; and a capacitor embedded in the passivation structure, wherein the capacitor includes first metal-insulator-metal (MIM) stacks inserted in first trenches, and second MIM stacks formed into first pillar structures.

Abstract: The present disclosure provides a redistribution structure that includes a metal line, a first dielectric layer disposed over the metal line, a first etch stop layer (ESL) disposed over the first dielectric layer, a second dielectric layer disposed over the first ESL, and a conductive via extending through the second dielectric layer, the first ESL and the first dielectric layer to contact the metal line. A lower portion of the second dielectric layer extends downward through the first ESL and the first dielectric layer and partially into the metal line.

Abstract: A passivation layer is formed over an interconnect structure. An opening is etched at least partially through the passivation layer. A first conductive layer is deposited over the passivation layer. The first conductive layer partially fills the opening. An insulator layer is deposited over the first conductive layer. The insulator layer partially fills the opening. A second conductive layer is deposited over the insulator layer. The second conductive layer completely fills the opening. A first conductive structure is formed that is electrically coupled to the first conductive layer. A second conductive structure is formed that is electrically coupled to the second conductive layer.

Abstract: One aspect of the present disclosure pertains to an integrated (IC) structure. The IC structure includes a semiconductor substrate; an interconnect structure formed over the substrate; and a redistribution layer (RDL) structure formed over the interconnect structure. The RDL structure includes: a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure; a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure; and a RDL top portion over the RDL pad portion and the RDL signal routing portion. The multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width, the sacrificial via having a sacrificial via width, and the block via width is greater than the sacrificial via width.

Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method includes forming a first conductive pad and a mask layer over the interconnect structure. The mask layer covers a top surface of the first conductive pad. The method includes forming a metal oxide layer over a sidewall of the first conductive pad. The method includes forming a second conductive pad over the first conductive pad and passing through the mask layer. The first conductive pad and the second conductive pad are made of different materials.

Abstract: A method for forming a semiconductor memory structure includes forming an MTJ stack over a substrate. The method also includes etching the MTJ stack to form an MTJ device. The method also includes depositing a metal layer over a top surface and sidewalls of the MTJ device. The method also includes oxidizing the metal layer to form an oxidized metal layer. The method also includes depositing a cap layer over the oxidized metal layer. The method also includes oxidizing the cap layer to form an oxidized cap layer. The method also includes removing an un-oxidized portion of the cap layer.