Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.

Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.

Abstract: A pick-resistant lock system includes a locking means. The locking means includes a displacement sensor for sensing displacement so as to generate a displacement signal, the displacement sensor comprising a micro electromechanical gyroscope, a second counterpart, a second alarm, and a second control unit for receiving the displacement signal so as to start the alarm. A key includes a control switch, a second counterpart corresponding to the second counterpart, a second alarm, and a second control unit for receiving the displacement signal transmitted from the locking means so as to start the second alarm.

Abstract: A pick-resistant lock system includes a locking means. The locking means includes a displacement sensor for sensing displacement so as to generate a displacement signal, the displacement sensor comprising a micro electromechanical gyroscope, a second counterpart, a second alarm, and a second control unit for receiving the displacement signal so as to start the alarm. A key includes a control switch, a second counterpart corresponding to the second counterpart, a second alarm, and a second control unit for receiving the displacement signal transmitted from the locking means so as to start the second alarm.

Abstract: A kind of terminal includes a base part, which is a planar shape. A connecting part extends from the back of the base part. A contact part extends from the front of the base part. The tip of the contact part forms a contact probe that has an arc surface. A pair of pass holes is defined on the left side and the right side of the base part. A region in the base part further protrudes upwards to form a lump as a press part and extends downwards to form an insertion part.