Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Abstract: A method includes manufacturing a plurality of wafers each having a substrate having an active surface and a backside, and a stop layer dividing the substrate into a first substrate part at a side of the active surface and a second substrate part at a side of the backside; on a first wafer of the plurality of wafers, removing the second substrate part and the stop layer; bonding a second wafer of the plurality of wafers on the first wafer with first substrate part of the second wafer facing a surface of the first wafer that is exposed by removing the stop layer and, on the second wafer, performing the same processes of removing the second substrate part and stop layer of the second wafer; repeating the bonding and removing the second substrate part and stop layer with one or more wafers to form a stack of wafers.

Abstract: A method for manufacturing a semiconductor structure with power connecting structures under transistors comprises: forming a stop layer structure in a semiconductor substrate to divide the semiconductor substrate into a first substrate part and a second substrate part; forming a plurality of stop portions in the first substrate part and in proximity to an active surface; arranging the transistor elements on the active surface, the contact portions of the transistor elements corresponding to the stop portions; removing the second substrate part and the stop layer structure; forming a first patterned mask layer with first patterned openings on a bottom surface of the first substrate part, the first patterned openings corresponding to the stop portions; forming through open slots in the first substrate part and exposing the contact portions via the open slots; forming a protecting layer to cover side walls of the open slots; forming a conductive layer to cover the contacts; and forming the power connecting struc

Abstract: A method for manufacturing a semiconductor structure with power connecting structures under transistors comprises: forming a stop layer structure in a semiconductor substrate to divide the semiconductor substrate into a first substrate part and a second substrate part; forming a plurality of stop portions in the first substrate part and in proximity to an active surface; arranging the transistor elements on the active surface, the contact portions of the transistor elements corresponding to the stop portions; removing the second substrate part and the stop layer structure; forming a first patterned mask layer with first patterned openings on a bottom surface of the first substrate part, the first patterned openings corresponding to the stop portions; forming through open slots in the first substrate part and exposing the contact portions via the open slots; forming a protecting layer to cover side walls of the open slots; forming a conductive layer to cover the contacts; and forming the power connecting struc

Abstract: A method includes manufacturing a plurality of wafers each having a substrate having an active surface and a backside, and a stop layer dividing the substrate into a first substrate part at a side of the active surface and a second substrate part at a side of the backside; on a first wafer of the plurality of wafers, removing the second substrate part and the stop layer; bonding a second wafer of the plurality of wafers on the first wafer with first substrate part of the second wafer facing a surface of the first wafer that is exposed by removing the stop layer and, on the second wafer, performing the same processes of removing the second substrate part and stop layer of the second wafer; repeating the bonding and removing the second substrate part and stop layer with one or more wafers to form a stack of wafers.

Abstract: A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first RDL, a second RDL, a contact feature, and a chip. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via. The second RDL is disposed over the back surface of the substrate and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the second RDL and electrically connecting to the trench capacitor through the second RDL. The chip is bonded over the front surface of the substrate. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first redistribution layer (RDL), a second RDL, and a contact feature. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via, wherein the active area is disposed between the trench capacitor and the first RDL. The second RDL is disposed over the back surface and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the first RDL and electrically connecting to the trench capacitor through the first RDL, the through via and the second RDL. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor structure includes a plurality of dies over a redistribution layer (RDL). A first die comprises: a first substrate; a first (RDL), disposed over a front surface of the first substrate; and a first back-side through via (BSTV), extending from a back surface of the first substrate toward the front surface of the first substrate. A second die, adjacent to the first die and separated from the first die by a molding material, comprises: a second substrate; a second RDL, disposed over a front surface of the second substrate; and a second BSTV, extending from a back surface of the second substrate toward the front surface of the second substrate. The RDL continuously covers the back surfaces of the first and second substrates, and electrically connects the first RDL to the second RDL via the first and second BSTVs. A method of manufacturing the semiconductor structure is also provided.

Abstract: A method for manufacturing a semiconductor stack structure with an ultra-thin die includes: forming a stop layer structure inside a semiconductor substrate by ion implantation, and then providing electrical components and an inner connection layer on an active surface of the semiconductor substrate to form a semiconductor wafer; enabling inner connection layers of two semiconductor wafers to be opposite and bonded together up and down; removing part of the semiconductor substrate and the stop layer structure of the upper one of the semiconductor wafers from a backside of the upper one of the semiconductor wafers through a backside grinding process and a thinning process, enabling the upper one of the semiconductor wafers to form a thinned semiconductor wafer; carrying out bonding, backside grinding and thinning processes on the other semiconductor wafer one by one on the thinned semiconductor wafer to stack another thinned semiconductor wafer upwards one by one; and finally, carrying out backside grinding and

Abstract: The present application discloses a semiconductor package, a semiconductor device, and a method for manufacturing a semiconductor package. The semiconductor package includes a silicon interposer, a redistribution layer (RDL) formed on the silicon interposer, and a plurality of computation nodes disposed on the RDL. Each of the computation nodes includes a computation dies and a plurality of high bandwidth memory dies. Each adjacent computation nodes can be coupled to each other through the RDL. The silicon interposer is a silicon wafer, and the semiconductor package is a wafer level package (WLP). Therefore, the computing power of the plurality of computation nodes can be embedded within one package, thereby achieving a system on wafer (SoW) that has greater computation capability within a smaller area.

Abstract: The present application discloses a semiconductor package and a method for manufacturing the semiconductor package. The semiconductor package includes a first dielectric layer, a first redistribution layer (RDL) disposed on a first surface of the first dielectric layer, a first bonding layer disposed on the first RDL, a plurality of bottom dies attached to the first bonding layer, a second dielectric layer filling gaps between the bottom dies, a plurality of conductive pillars disposed in the second dielectric layer without contacting the bottom dies, a second RDL disposed on the second dielectric layer and the bottom dies, a second bonding layer disposed on the second RDL, a plurality of top dies attached to the second bonding layer, a third dielectric layer filling gaps between the top dies, and a plurality of solder bumps disposed on a second surface of the first dielectric layer.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes at least one bottom die and a plurality of top dies. The semiconductor structure further includes a redistribution layer (RDL) formed on the at least one bottom die, and a plurality of micro bumps formed on the RDL. The top dies is stacked on the bottom die with their front sides being attached to the micro bumps. The RDL allows communication between a top die and the bottom die and allows the communication between adjacent top dies. The die-stacking structure enables greater computation capability within a smaller area.

Abstract: The present application discloses a semiconductor package and a method for manufacturing a semiconductor package. The semiconductor package includes a plurality of bottom dies and a plurality of top dies stacked on the bottom dies with a first RDL in between, thereby embedding more computation power within one semiconductor package and enabling flexible routing between dies. In addition, the top dies and the bottom dies are stacked in a face-to-face manner so the signal paths between the top dies and the bottom dies can be shortened, and thus, the IR drop of the transmission between dies can be reduced.

Abstract: This disclosure relates to a polishing composition that includes an abrasive, at least two pH adjusters, a barrier film removal rate enhancer, a low-k removal rate inhibitor, and an azole-containing corrosion inhibitor. This disclosure also features a method of using the polishing composition to polish a substrate containing copper and silicon oxide.

Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

Abstract: A method for manufacturing a semiconductor structure with power connecting structures under transistors comprises: forming a stop layer structure in a semiconductor substrate to divide the semiconductor substrate into a first substrate part and a second substrate part; forming a plurality of stop portions in the first substrate part and in proximity to an active surface; arranging the transistor elements on the active surface, the contact portions of the transistor elements corresponding to the stop portions; removing the second substrate part and the stop layer structure; forming a first patterned mask layer with first patterned openings on a bottom surface of the first substrate part, the first patterned openings corresponding to the stop portions; forming through open slots in the first substrate part and exposing the contact portions via the open slots; forming a protecting layer to cover side walls of the open slots; forming a conductive layer to cover the contacts; and forming the power connecting struc

Abstract: A method of manufacturing a three-dimensional system-on-chip, comprising providing a memory wafer structure with a first redistribution layer; disposing a first conductive structure and a core die structure and an input/output die structure with a second conductive structure on the first redistribution layer, the input/output die structure being disposed around the core die structure; forming a dielectric layer covering the core die structure, the input/output die structure, and the first conductive structure; removing a part of the dielectric layer and thinning the core die structure and a plurality of input/output die structures to expose the first and second conductive structures; forming a third redistribution layer on the dielectric layer, the third redistribution layer being electrically connected to the first and second conductive structures; forming a plurality of solder balls on the third redistribution layer; performing die saw. A three-dimensional system-on-chip is further provided.