Abstract: Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Improved gate structures, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; a gate electrode over the high-k dielectric layer; a conductive cap over and in contact with the high-k dielectric layer and the gate electrode, a top surface of the conductive cap being convex; and first gate spacers on opposite sides of the gate structure, the high-k dielectric layer and the conductive cap extending between opposite sidewalls of the first gate spacers.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.