Patents by Inventor Tzu-Wen Wang

Tzu-Wen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250089321
    Abstract: A silicon substrate structure has a substrate, a first groove, a second groove and a third groove. The substrate includes a first surface and a second surface. The first surface is formed on one side of the Si(111) lattice plane, and the second surface is formed on the opposite side of the Si(111) lattice plane. The first groove is disposed along a first direction on the second surface. The second groove is disposed along a second direction on the second surface. The third groove is disposed along a third direction on the second surface. The first direction is defined as the direction from the Si(111) lattice plane to the Si(1-1-1) lattice plane, the second direction is defined as the direction from the Si(-11-1) lattice plane to the Si(1-11) lattice plane, and the third direction is defined as the axial direction of the Si[1-10] lattice orientation.
    Type: Application
    Filed: February 28, 2024
    Publication date: March 13, 2025
    Inventors: Po-Jen HSIEH, Tzu-Wen WANG
  • Patent number: 12243967
    Abstract: A pixel package includes an electrode structure, a plurality of light-emitting units arranged on the electrode structure, and a light transmitting layer. The electrode structure has an upper layer with a first upper sheet, a lower layer with a first lower sheet, and a supporting layer arranged between the upper layer and the lower layer. The electrode structure and the plurality of light-emitting units are fully embedded in the light transmitting layer. In a top view of the pixel package, the first upper sheet is overlapped with and larger than the first lower sheet.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 4, 2025
    Assignees: Epistar Corporation, Yenrich Technology Corporation
    Inventors: Chi-Chih Pu, Li-Yuan Huang, Tzu-Hsiang Wang, Ya-Wen Lin
  • Publication number: 20250058412
    Abstract: A laser welding mechanism includes a main body having a space and two securing devices which are respectively attached to two ends of the body. A linkage assembly includes a bearing and a linkage tube. A refraction mirror unit includes two mirrors connected to the linkage tube of the linkage assembly. A laser unit is pivotally connected to a swinging member which is connected to the linkage tube of the linkage assembly. A drive unit including a motor, a driving gear, and a driven gear. A rotation unit is connected to the swinging member of the laser unit. The laser unit rotates relative to the first workpiece and the second workpiece during welding, ensuring a stable rotation at the joining faces of the two workpieces.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 20, 2025
    Inventors: KUO CHIANG TSENG, NAN KAI WENG, CHIH YU WENG, PEI YU WANG, TZU WEN SUNG, FENG CHI WEI, MAO TE CHUANG
  • Patent number: 12218670
    Abstract: An integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors in at least one strong active-region structure. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented with weak transistors in at least one weak active-region structure. The integrated circuit further includes a first inverter cross coupled with the first clocked inverter and a second inverter cross coupled with the second clocked inverter. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Wen Wang, Po-Chih Cheng, Jia-Hong Gao, Kuang-Ching Chang, Tzu-Ying Lin, Jerry Chang Jui Kao
  • Patent number: 12204163
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: January 21, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240222548
    Abstract: The present invention provides a light emitting diode, which includes a substrate, a first intermediary layer and a two-dimensional material structure. The first intermediary layer is located on the substrate. The two-dimensional material structure is located on the first intermediary layer, and the two-dimensional material structure is formed by stacking a plurality of two-dimensional material layers. The number of the plurality of two-dimensional material layers is not less than 2. The light with a specific wavelength is emitted or absorbed by the two-dimensional material structure.
    Type: Application
    Filed: November 2, 2023
    Publication date: July 4, 2024
    Inventors: Yi-Jen LIN, Yen-Chun TSENG, Tzu-Wen WANG
  • Publication number: 20240194773
    Abstract: The present invention provides a high electron mobility transistor, which includes a substrate, a buffer layer, a channel layer, a first semiconductor epitaxial structure, a second semiconductor epitaxial structure, a drain, a source and a gate. The first semiconductor epitaxial structure is located on the channel layer and sequentially includes a first aluminum gallium nitride layer, a supply layer and a second aluminum gallium nitride layer, and the first semiconductor epitaxial structure is formed with a hollow part extending from a top surface of the second aluminum gallium nitride layer toward the channel layer. The second semiconductor epitaxial structure is located in the hollow part and sequentially includes an aluminum gallium nitride layer and a P-type gallium nitride layer. The drain and the source are respectively arranged on the second aluminum gallium nitride layer, and the gate is arranged on the P-type gallium nitride layer.
    Type: Application
    Filed: October 26, 2023
    Publication date: June 13, 2024
    Inventors: Yen-Chun TSENG, Tzu-Wen WANG, Chuan-Wei CHEN
  • Publication number: 20240194774
    Abstract: The present invention provides a high electron mobility transistor, which includes a substrate, a buffer layer, a gallium nitride layer, a two-dimensional material structure, a covering layer, a drain, a source and a gate. The buffer layer is located on the substrate. The gallium nitride layer is located on the buffer layer and forms a channel layer. The two-dimensional material structure is located on the channel layer. The covering layer partially covers the two-dimensional material structure. The drain and the source are arranged on the two-dimensional material structure, and the gate is arranged on the covering layer.
    Type: Application
    Filed: November 2, 2023
    Publication date: June 13, 2024
    Inventors: Yen-Chun TSENG, Tzu-Wen WANG, Chuan-Wei CHEN
  • Patent number: 11411136
    Abstract: A micro light-emitting diode (micro-LED) chip adapted to emit a red light or an infrared light is provided. The micro-LED chip includes a GaAs epitaxial structure layer, a first electrode, and a second electrode. The GaAs epitaxial structure layer includes an N-type contact layer, a tunneling junction layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, and an N-type window layer along a stacking direction. The first electrode electrically contacts the N-type contact layer. The second electrode electrically contacts the N-type window layer.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 9, 2022
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Tzu-Wen Wang, Hsin-Chiao Fang
  • Publication number: 20210367105
    Abstract: A micro light-emitting diode (micro-LED) chip adapted to emit a red light or an infrared light is provided. The micro-LED chip includes a GaAs epitaxial structure layer, a first electrode, and a second electrode. The GaAs epitaxial structure layer includes an N-type contact layer, a tunneling junction layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, and an N-type window layer along a stacking direction. The first electrode electrically contacts the N-type contact layer. The second electrode electrically contacts the N-type window layer.
    Type: Application
    Filed: October 21, 2020
    Publication date: November 25, 2021
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Tzu-Wen Wang, Hsin-Chiao Fang
  • Publication number: 20180006189
    Abstract: An epitaxial structure with a tunnel junction, a p-side up processing intermediate structure and a manufacturing method thereof are provided. The epitaxial structure includes: a substrate, a first n-type semiconductor layer, a tunnel junction layer, a p-type semiconductor layer, a multiple quantum well layer and a second n-type semiconductor layer, wherein the first n-type and p-type semiconductor layers and the tunnel junction layer together form a p-type semiconductor structure. The manufacturing method of the p-side up processing intermediate structure includes disposing a permanent substrate on the second n-type semiconductor layer to form a laminated structure, flipping the laminated structure upside down and removing the substrate of the epitaxial structure, thereby resulting in the p-type semiconductor structure being disposed facing up.
    Type: Application
    Filed: February 14, 2017
    Publication date: January 4, 2018
    Inventors: Tzu-Wen Wang, Wei-Yu Tseng
  • Publication number: 20120037500
    Abstract: A hollow target assembly has a support tube, a target body and a plurality of elastic elements. The target body includes a plurality of hollow target materials and they pass through the support tube sequentially and locate at the outer surface of the support tube. By the grooves formed and extended from an end of the inside wall of the hollow target material and the corresponding concaves formed at the outside wall of the support tube, the elastic elements can lean and be positioned in the space generated by the grooves and corresponding concaves. Therefore, the target body and the support tube are brought together closely by these elastic elements in a simple and a low-cost way.
    Type: Application
    Filed: August 12, 2010
    Publication date: February 16, 2012
    Applicant: SOLAR APPLIED MATERIALS TECHNOLOGY CORP.
    Inventors: Chung-Han WU, Kuan-Ting Lai, Tzu-Wen Wang
  • Publication number: 20100170786
    Abstract: A method for making a refurbished sputtering target has steps of providing a spent target with a backside, an eroded side and a rim; mechanically pre-treating the backside of the spent target; applying powder material that has the same composition as the spent target to form a powder-filled layer; and sequentially pre-pressing and sintering the spent target with the powder-filled layer to obtain the refurbished sputtering target. Therefore, a percentage of the spent target is reduced by mechanically treating the backside of the spent target, so the refurbished sputtering target has a consistent quality.
    Type: Application
    Filed: July 6, 2009
    Publication date: July 8, 2010
    Applicant: SOLAR APPLIED MATERIALS TECHNOLOGY CORP.
    Inventors: Tzu-Wen WANG, Chih-Yao CHAN, Hao-Chia LIAO
  • Patent number: D606160
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: December 15, 2009
    Inventor: Tzu-Wen Wang