Abstract: A power supply circuit for stably supplying power to loads of a vehicle comprises a battery pack, a switch circuit, a first control circuit, a detection circuit, and a second control circuit. The first control circuit is configured to output a first control signal to turn on the switch circuit and the battery pack can supply power to the loads when the vehicle is in a first state. The detection circuit is configured to detect whether the first control circuit normally outputs the first control signal during the first state and output a trigger signal to the second control circuit in response to the first control circuit does not output the first control signal. The second control circuit outputs a second control signal according to the trigger signal to control the switch circuit to be turned on. A power supply method and the vehicle are also disclosed.

Abstract: Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.

Abstract: Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer etching is performed from the backside to an etch stop layer deposited over the front side of the substrate.

Abstract: Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.

Abstract: A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.

Abstract: Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.

Abstract: A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.

Abstract: A method of patterning an indium tin oxide film includes the steps of forming a cap layer over the indium tin oxide film and subjecting exposed areas of the indium tin oxide film to a water plasma.

Abstract: A method for releasing a micromechanical structure. A substrate is provided. At least one micromechanical structural layer is provided above the substrate, wherein the micromechanical structural layer is sustained by a sacrificial layer of a silicon material. An amine-based etchant is provided to etch the silicon material. That is, during performing a post-cleaning procedure with an amine-based etchant, polymer residue and the sacrificial layer of silicon can be simultaneously removed without any additional etching processes.

Abstract: Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer etching is performed from the backside to an etch stop layer deposited over the front side of the substrate.

Abstract: Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.

Abstract: An MEMS mirror structure is formed using an etching process that forms sidewall oxide spacers while maintaining the integrity of the oxide layer formed over the reflective layer of the MEMS mirror structure. The discrete mirror structure is formed to include a reflective layer sandwiched between oxide layers and with a protect layer formed over the upper oxide layer. A spacer oxide layer is formed to cover the structure and oxide spacers are formed on sidewalls of the discrete structure using a selective etch process that is terminated when horizontal portions of the spacer oxide layer have cleared to expose the release layer formed below the discrete mirror structure and the protect layer. The superjacent protect layer prevents the spacer oxide etch process from attacking the upper oxide layer and therefore maintains the integrity of the upper oxide layer and the functionality of the mirror structure.

Abstract: A capacitor structure which has generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the at least one dielectric layer. The second conductive layer has a second area which is less than the first area of the at least one dielectric layer. A method of fabricating a capacitor structure is also disclosed.

Abstract: A method for releasing a micromechanical structure. A substrate is provided. At least one micromechanical structural layer is provided above the substrate, wherein the micromechanical structural layer is sustained by a sacrificial layer of a silicon material. An amine-based etchant is provided to etch the silicon material. That is, during performing a post-cleaning procedure with an amine-based etchant, polymer residue and the sacrificial layer of silicon can be simultaneously removed without any additional etching processes.

Abstract: An in-situ performed method utilizing a pure H2O plasma to remove a layer of resist from a substrate or wafer without substantially accumulating charges thereon. Also, in-situ performed methods utilizing a pure H2O plasma or a pure H2O vapor to release or remove charges from a surface or surfaces of a substrate or wafer that have accumulated during one or more IC fabrication processes.

Abstract: A capacitor structure which has generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the at least one dielectric layer. The second conductive layer has a second area which is less than the first area of the at least one dielectric layer. A method of fabricating a capacitor structure is also disclosed.

Abstract: An pure H2O stripping process for etched metal wafers effectively solves the metal corrosion deficiencies induced by O2, N2 plasma charging. The pure H2O plasma stripping releases and neutralizes the storage of positive charge accumulated in the wafer, reduces chlorine concentration, and effectively strips the photoresist and etching residue. Thereby reducing metal corrosion and increases the anti-metal corrosion window. The pure H2O plasma stripping requires no additional equipment and or steps.

Abstract: A mirror process uses a tungsten passivation layer to prevent metal-spiking induced mirror bridging and improve mirror curvature. A mirror structure is patterned on a first sacrificial layer overlying a substrate. A tungsten passivation layer is then blanket deposited to cover the top and sidewalls of the mirror structure. A second sacrificial layer is formed overlying the tungsten passivation layer. A releasing process with an etchant including XeF2 is performed to remove the second sacrificial layer, the tungsten passivation layer and the first sacrificial layer simultaneously.

Abstract: An in-situ method of stripping a layer of resist from a substrate or wafer utilizes pure H2O plasma recipe to substantially prevent charges from accumulating on the substrate or wafer during stripping of the layer of resist.

Abstract: An MEMS mirror structure is formed using an etching process that forms sidewall oxide spacers while maintaining the integrity of the oxide layer formed over the reflective layer of the MEMS mirror structure. The discrete mirror structure is formed to include a reflective layer sandwiched between oxide layers and with a protect layer formed over the upper oxide layer. A spacer oxide layer is formed to cover the structure and oxide spacers are formed on sidewalls of the discrete structure using a selective etch process that is terminated when horizontal portions of the spacer oxide layer have cleared to expose the release layer formed below the discrete mirror structure and the protect layer. The superjacent protect layer prevents the spacer oxide etch process from attacking the upper oxide layer and therefore maintains the integrity of the upper oxide layer and the functionality of the mirror structure.